STLEP0IN
Meaning:
Return the STALL handshake in response to an IN request to endpoint 0.
Location:
EPSTALLS.0
Set:
The CPU sets this bit to instruct the SIE to return the STALL handshake for an IN
request directed to endpoint 0.
Clear:
The SIE clears this bit whenever a SETUP token arrives.
POR:
STLEP0IN=0
Chip Reset:
STLEP0IN=0
Bus Reset:
STLEP0IN=0
Pwr Down:
Read-only
Programming Notes:
The CPU sends the STALL handshake to indicate an illegal or unknown request to endpoint 0.
Endpoint 0 has three stall bits to account for the status stage, and the optional IN and OUT data
stages that the transfer may use:
•
•
STLEP0IN
•
If a CONTROL transfer is to be stalled, both the data stage (if present) and the status stage
should receive the STALL handshake. Since all three stall bits are cleared with the arrival of the
next SETUP token, the best way to stall any CONTROL transfer is to set all three endpoint 0
stall bits. This will correctly stall all stages of any CONTROL transfer that the host may send.
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