IN2BAVIRQ
Meaning:
Endpoint 2-IN Buffer Available Interrupt Request
.
Location:
EPIRQ.3
Set:
The SIE sets this bit after receiving an IN token directed to Endpoint 2, sending
the data in the EP2INFIFO (page 18) and receiving the ACK handshake from the
host. This indicates that the EP2INFIFO is again available for loading by the
CPU.
Clear:
The CPU resets this bit by writing the byte count register EP2INBC (page17).
.
POR:
IN2BAVIRQ=1
Chip Reset:
IN2BAVIRQ=1
Bus Reset:
IN2BAVIRQ=1
Pwr Down:
Read-only
Programming Notes:
EP2IN is a double-buffered endpoint, meaning that it uses two FIFOS and byte count registers.
Double buffering allows USB data simultaneously to move out of one IN FIFO while the CPU
loads data into the other. This improves bandwidth performance in many systems.
The IN2BAVIRQ flag logic makes the double buffering invisible to the programmer. For
example, assume that both buffers are available and therefore IN2BAVIRQ=1. The CPU writes
N bytes to the EP2INFIFO, and then arms the transfer by writing N to the EP2INBC register. For
a single buffered IN endpoint, nothing would happen until the host sent the IN token to the
endpoint and accepted the IN data packet. But because the second buffer is available for CPU
loading the IN2BAVIRQ bit goes invalid and immediately goes valid again, just as if the first
packet had already been sent and accepted by the host.
The double buffering action also means that after the MAX3420E is reset, the IN2BAVIRQ bit
remains set until the EP2INBC register is loaded twice.
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