Lexicon RV-8, Service Manual

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used in the released version of this product, and therefore is installed during software development cycles
only.
Emulator Support (J14)
The Emulator socket is designed to accept a 40-position emulator pod for boot code development. When
the pod is in place, it acts exactly like the EEPROM mentioned above. The
BOOTCS/ signal is routed to
the chip enable pin by placing a jumper plug between pins 2 and 3 on W5. This device is not used in the
released version of this product, and therefore is installed during software development cycles only.
Reset Generator (U31)
The Reset Generator provides reliable one-shot pulses of both polarities to various components on the
Main Board and to all off-board peripheral devices that are required to initialize to a known state when
power is first applied. These pulses are approximately 3mS in duration, from the time that power is first
applied. The time constant is set by the value of C116, and is determined by the equation:
T
B D B
= (2.6 x 10
P
4
P
) x C112
Where: T
B
D
B
is in seconds, C112 is in Farads.
Resistor R111 serves to eliminate false triggering of the output pulse by limiting the current flowing into
the
CT pin (3). This impacts the T
B D B
value minimally, by slowing the rise time of the output pulse.
Generally, this is not critical, and therefore can be ignored. R110 provides a default pull-up of the RESIN/
pin (2), thereby enabling the reset circuit to work as intended. A test point (E6) has been provided so that
manual triggering of the reset may be accomplished by connecting the test point to ground momentarily.
This saves the trouble of having to power cycle the entire unit. C111 provides high frequency filtering of
the internal voltage reference at the
REF pin (1). R113 provides a default pull-up for the RESET/ pin (5)
while R112 provides a default pull-down of the RESET pin (7). C114 is a standard power supply
decoupling capacitor.
Buffers, Level Shifters (Sheet 2)
This sheet contains a set of external registers for software control of certain external resources, as well as
level shifters interfacing the 5V and 3.3V domains.
Level Shifters (U36 and U37)
U37 is a bidirectional transceiver hardwired for signal flow from the A ports to the B ports. Signals
originating from the 3.3V domain are given a shift in level, making them compatible with the CMOS 5 volt
threshold of the CPU input pins. Five of the interrupt sources discussed in the previous section are
sourced from the FPGA directly to the processor after undergoing level shifting. U36 performs a similar
function with a byte wide data bus between the FPGA and the CPU. It should be noted that the FPGA is 5
volt tolerant on all of it’s I/O, and therefore needs not to have any 5V level signals attenuated to 3.3V.
When a memory access is made to the CS2/ space of the CPU, U36 is taken out of tristate and becomes
active. The BUFDIR signal as generated by the FPGA controls the direction flow of this device, that is to
say signal flow is from the CPU to the FPGA during write cycles, and from the FPGA to the CPU during
read cycles.
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