+5VD
YEL
RED
GRN
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
DIR
GND
VCC
G
74VHCT245
+3.3VD
+3.3VD
150
150
150
150
150
DESCRIPTION
REV
CHECKER
DRAFTER
AUTH.
Q.C.
REVISIONS
1
SIZE
OF
3
2
A
B
C
D
1
2
3
4
5
6
7
8
4
5
6
7
8
A
B
C
D
NUMBER
CODE
Q.C.
ISSUED
DATE
APPROVALS
CONTRACT
NO.
SHEET
FILE NAME
B
DRAWN
CHECKED
TITLE
exicon
REV
3 OAK PARK
BEDFORD, MA 01730
150
74VHC273
CLR
CLK
7D
6D
5D
4D
3D
2D
8Q
7Q
4Q
3Q
2Q
5Q
6Q
1D
1Q
8D
GND
VCC
74VHC273
CLR
CLK
7D
6D
5D
4D
3D
2D
8Q
7Q
4Q
3Q
2Q
5Q
6Q
1D
1Q
8D
GND
VCC
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
DIR
GND
VCC
G
74VHCT245
+5VD
GRN
RED
YEL
+5VD
+5VD
74ACT244
A1
A2
A3
Y2
Y3
Y4
GND
G
A4
Y1
VCC
74ACT244
A1
A2
A3
Y2
Y3
Y4
GND
G
A4
Y1
VCC
+5VD
ECM
10/9/03
MAG
10/9/03
CAM
10/2/03
CHANGED PER DCR 030626-00
RWH
9/29/03
MAG
5/20/03
5/20/03
CW
5/2/03
RWH
CAM
5/14/03
2
CHANGED PER DCR 030307-00
SPARES
MAG
12/20/02
12/20/02
CW
11/06/02
CAM
11/05/02
RWH
1
CHANGED PER DCR 020913-00
4/26/02
4/30/02
5/1/02
4/30/02
JV
CW
CAM
RWH
SCHEM, MAIN BD,RV8
060-15559
.
BUFFERS, LEVEL SHIFTERS
CPU TEST LEDS
3
3
2
19
15559-6
5-
6-
2004_9:
30
2
NC
AMP_RESET/
[12/B8]
11
13
15
7
5
3
10
19
17
9
20
U45
2
4
6
16
14
12
10
1
8
18
20
U45
FPGA_RESET/
[9/C8]
VIDEO_RESET/
[12/B4]
FP_RESET/
[12/B6]
D12
D11
D10
MAINS_RLY
[12/A4]
CPUCS2/
[1/B3,9/C8]
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
19
1
18
20
10
U37
20
10
18
2
3
15
12
5
6
9
16
19
4
7
8
13
14
17
11
1
U21
1
11
17
14
13
8
7
4
19
16
9
6
5
12
15
3
2
18
10
20
U20
CPU_TEST_LED1
CPU_TEST_LED[6:1]
CPU_TEST_LED1
CPU_TEST_LED2
CPU_TEST_LED3
CPU_TEST_LED4
CPU_TEST_LED6
CPU_TEST_LED5
CPU_TEST_LED6
CPU_TEST_LED5
CPU_TEST_LED4
CPU_TEST_LED3
CPU_TEST_LED2
CPU_TEST_LED6
CPU_TEST_LED1
CPU_TEST_LED2
CPU_TEST_LED3
CPU_TEST_LED4
CPU_TEST_LED5
BOOT_LOCK
[1/A3]
NC
CPU_WRDCLK_MON
[1/A3]
NC
R36
SOFT_RLY
[12/A4]
[7/B3]
RESREGDECH
BUFDIR
[9/D2]
NC
REMOTE_PWREN1
[14/C7]
REMOTE_PWREN0
[14/C7]
NC
RESREGDECL
[7/B3]
CPUDATA12
CPUDATA[15:0]
[1/D3,7/A5]
CPUDATA6
CPUDATA3
CPUDATA2
CPUDATA1
CPUDATA0
CPUDATA4
CPUDATA5
CPUDATA7
CPUDATA8
CPUDATA9
CPUDATA10
CPUDATA11
CPUDATA13
CPUDATA15
CPUDATA14
CPUDATA0
CPUDATA7
CPUDATA6
CPUDATA5
CPUDATA4
CPUDATA3
CPUDATA2
CPUDATA1
LVDATA[15:0]
[9/D3]
LVDATA2
LVDATA0
LVDATA1
LVDATA7
LVDATA6
LVDATA5
LVDATA4
LVDATA3
LVVIDTUNIRQ/
[9/C2]
LVCRYIRQ/
[9/C2]
LVDSPABIRQ/
[9/D2]
LVKYBDIRQ/
[9/D2]
WRDCLKMON
[9/C8]
CPU_VIDTUNIRQ/
[1/D8]
CPU_CRYIRQ/
[1/C8]
CPU_DSPABIRQ/
[1/B8]
CPU_KYBDIRQ/
[1/B8]
EXPB_RESET/
[10/A6]
EXPA_RESET/
[10/A8]
CRY_RESET/
[8/D6]
DSPBRESET/
[3/B8]
DSPARESET/
[3/C8]
R33
R32
R31
R34
R35
NC
10
20
18
1
19
11
12
13
14
15
16
17
9
8
7
6
5
4
3
2
U36
D13
D14
D15
1
2
3
4
5
6
7
8
9
*
J10
IAMP_SOFT_RLY
IAMP_SOFT_RLY
IAMP_MAINS_RLY
IAMP_MAINS_RLY
RESET/
[1/A3]
NC
NC
NC
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