Lexicon RV-8, Service Manual

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difference level around 0Vdc. The converted input video is introduced into the component-video relay tree
and is a selectable output just as any Y Pb Pr component input.
The encoder within U34 produces the complete video waveform for normal NTSC or PAL video inputs.
However, during trick modes of VCR playback (pause, shuttle), the sync portion of the video is derived
from a logic signal HVSYNC/. CPLD U14 detects trick modes based on anomalies in the decoded video
sync timing. With normal video, the PLAYSPEED signal is asserted high. In trick modes, PLAYSPEED is
not asserted, and system software in the host asserts SYNC_EN. U2, Q20, and associated circuitry
switch U4 during sync time to construct a video waveform with sync derived from HVSYNC/.
There is time-base instability inherent with a VCR even in normal playback. To improve the stability of the
converted video output, a phase-locked loop (U1, sheet 9) is used to reduce abrupt frequency shifts of the
encoder clock ENC_27MHZ. A multiplexer within U14 determines whether ENC_27MHZ comes from the
PLL or directly from XCLK, according to a multiplexer within U14. The preferred clock is dependent on the
particular display device.
U34 is clocked at 24.576MHz by U33. Proper operation of the codec depends on the settings of an
extensive set of internal registers of both the decoder and encoder. These registers are read and written
via the I2C ports, connected to the host processor on the Main Board via J20 (sheet 10).
Component Video Switcher (Video board schematic sheet 3)
Component video switching is performed by means of relays to maximize signal fidelity and format
compatibility. There is no active circuitry in the video path of external component sources.
Three sets of component input rca jacks (component inputs 1,2,3) feed a 3-wide, two-tier tree of double-
throw relays. Each tier is comprised of a pair of dpdt relays. The tree selects one of the input sets and
presents it to the bank of final output relays. The final tier of relays (RY3,RY1) connects the output RCA
jacks either to the selected component input or to the video converter. One transistor driver is associated
with each pair of relays. Relays are actuated when the associated PSELn bit is asserted high, switching
from the normally-closed to the normally-open circuits.
Component OSD in the RV-8 is implemented through the video converter, which decodes the S-video
OSD and produces the Y Pb Pr component OSD.
One normally-open pole of RY2 disconnects the luminance component CNV_Y in order to effectively
disable component output.
The signals generated by the RV-8 OSD are compatible only with the 480i Y Pb Pr component format.
When incompatible formats are in use, the component OSD is inapplicable, and is not accessed by the
operating system software.
On-Screen Display Signals (Video board schematic sheet 5)
OSD chip U26 produces a character-based video display that can be overlaid on program video or that
can occupy a full-screen, based on an independent internal video generator. OSD modes and parameters
are controlled by an extensive set of internal registers, accessed via serial interface.
The character strings to be displayed are loaded serially into the screen memory within the chip. The
bitmapped patterns that define the shapes of individual characters are stored in external font memory,
interfaced through the A[15:0] and D[7:0] buses (see below). Character dot-clock is fixed at about 15
MHz, based on the external LC circuit formed by L7/C99/C100. A crystal clock is supplied by oscillator
U37 (PAL) or U36 (NTSC). The active oscillator is determined by a high level on either NTSC_EN or
PAL_EN, enabling the respective oscillator.
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