Lexicon RV-8, Service Manual

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Lexicon
The regulator provides the external 12VDC when the ON/OFF pin is brought to a logic 0. This pin is
software controlled via the external registers on sheet 2. See page 6-23 for further information. Inverter
U14 permits us to use positive logic in the software register.
This circuit is duplicated exactly with U9 and all associated components.
VCO A (Sheet 15)
The purpose of the VCO is to provide clean, stable clock that matches the average properties of a
potentially unstable reference, such as jitter. At the heart of the circuit is the metal-encased VCO module,
which provides an output clock at 22.579MHz or 24.576MHz depending on the control voltage. The
control voltage should fall between 5V and 6V.
The 700mVpp output of the VCO is amplified by one gate of U10 to a 5V logic level. This gate is self-
biased in the middle of its inverting characteristic by R41, R42, and C49. Another gate of U10 is used to
invert and buffer the output signal of the conditioning circuit. R43 provides source impedance termination
to reduce overshoot.
The output of the VCO is sent to the AVRX FPGA via MAIN_PLL_MCKO . This is used as a 512FS
master clock in 44kHz or 48kHz mode, and a 256FS master clock at 96KHz. The FPGA divides this clock
down to 44/48/96kHz and the result is phase and frequency compared to a corresponding frequency from
a selected reference, such as the derived clock from an S/PDIF stream or the local crystal oscillator.
When
MAIN_PLL_MCKO is too low relative to this reference, the FPGA generates a series of active low
pulses to the PLL Error Amplifier U11 via MAIN_PLL_PUMP_DN/ . If MAIN_PLL_MCKO is too high
relative to the reference, the FPGA generates a series of active high pulses to the PLL Error Amplifier via
MAIN_PLL_PUMP_UP .
The PLL Error Amplifier U11 is biased at 2.5V via the voltage divider comprised of R38 and R39. The
pump up/down pulses from the FPGA are buffered by U19 and connected to schottky diodes D18 and
D19. When no pulses are asserted, the diodes are reverse biased and no current is injected into the
summing node of U11. When the VCO frequency is too low, D16 will be forward biased by the
UPA/
pulses, asserted low by U19. The resulting current through R46 will be integrated by feedback capacitors
C41 and C42. This will cause a progressively higher voltage at test point VCOVA. This is the control
voltage to the VCO module; as this voltage rises, it causes the VCO output frequency to increase. R40
smoothes out the transient response of the feedback loop.
When MAIN_PLL_MCKO has reached equilibrium with the reference clock, the pump up/down signals
are inactive. The FPGA delivers a series of active low pulses to the error amplifier via
MAIN_PLL_LOCK_DN/ . The average duty cycle of these pulses is approximately 1/128. Instabilities such
as jitter in the reference will appear as variations in pulse width, but the instantaneous variation gets
averaged by the action of the loop filter. The result is a steady control voltage to the VCO that produces a
high stability frequency based on the average frequency of the reference.
When a lock down pulse forward biases D20, current flows through R48, which is integrated by C48. R49
provides a constant current of opposite polarity, which also gets integrated. The two integrals oppose
each other, and when the net current into the summing node is zero, the voltage at U11 pin 1 remains
constant. If the duty cycle of the pulse is too small, the voltage is driven progressively lower. If the duty
cycle is too high, the voltage is driven progressively higher. The resultant voltage is applied to R47, which
sinks current from the summing node of the loop integrator, which raises the VCO control voltage. This
gets counter-acted by current pulses through D17 and R44. When the integral of these two currents
balance, the control voltage remains constant, so the VCO output frequency remains constant, and the
loop is stabilized and locked.
6-45