Lexicon RV-8 Service Manual Download

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Lexicon

Audio Input Port

Signals: DEC_IN_FSI, DEC_IN_SCKI, DEC_SDI

This port takes as input I

S audio data

DEC_SDI

synchronous with

DEC_IN_SCKI

. A frame start pulse is

also utilized,

DEC_IN_FSI

. These signals are sourced from the AVRX FPGA. This data is multiplexed into

the Format Decoder from one of two sources. I

S data may come from the Main zone S/PDIF input block

or from one of six ADCs on the Analog I/O Board.

Chip Clock

Signals: CLK12500C, XTALO, PLLVDD, FILT1. FILT2, CLKSEL, PLLVSS

There are two possible methodologies of providing a global clock signal to the Format Decoder. The
default topology consists of U30, a 12.288MHz 3.3V oscillator. R107 places the output of U30 into the
path of the

CLKIN

pin. R108 ties the oscillator enable high, causing it to generate the clock.

The second clock source is from the system clock signal

CLK12500C

. R106 would pass this clock signal

along to the Format Decoder in this option. Naturally, the other two options would have to be disabled and
taken out of the path. This topology has been determined to be not practical due to the differences in
internal topologies between the Format Decoder and the SHARCs. As a result, this option is not
implemented.

FB13 provides a high frequency filtered version of the 2.5VA supply, which in turn is a high frequency
filtered version of the digital 2.5V supply. This double filtered supply voltage drives the internal Phase
Lock Loop of the Format Decoder at the

PLLVDD

pin. C100 provides local bulk capacitance for this

supply rail through the

FILT1

pin.

The internal PLL circuitry requires external band-pass filtering, which is provided via the

FILT2

pin by

R99, C98, and C99.

CLKSEL

selects the source clock for all internal logic in the Format Decoder, and is controlled by

software. When this signal is low, the internal clock source is the internal PLL. When high, then all internal
logic is driven by the

CLKIN

pin directly. This signal is significant during the boot phase of RV-8 when the

algorithm FLASH U19 is being loaded. Writing to this FLASH can only happen reliably when

CLKSEL

high.

PLLVSS

is connected to digital ground. This is the ground return pin for the internal PLL.

SDRAM Interface

Signals: SD_CS/, SDCKE/, SDCLKI, SDCLKO, DQM0/, DQM1/, SD_CAS/, SD_RAS/, SDWE/

SDRAM is not implemented for the Format Processor. As such, these pins are all pulled high by RP5,
RP6, and RP7.

FLASH Interface

Signals: CRY_NVCS/, CRY_NVWE/, CRY_FLCS/, CRY_NVOE/, DELWE/, NVCS, CRY_A[19:0],
CRY_D[7:0], GPIO20, GPIO21

The format processor utilizes a 512Kx8 FLASH RAM (U19) for algorithm storage. The algorithms are
loaded into the FLASH during the boot phase. Due to a bug in the silicon for the CS49400, the write
enable for the FLASH must be delayed approximately 10nS in relation to the address bus

CRY_A[19:0]

This is accomplished by R50/C21 which slows down the falling edge of

CRY_NVWE/

, effectively delaying

it by approximately 5nS. This signal is OR’ed with the original

CRY_NVWE/

to better align the rising edge

DELWE/

with the address bus so that the hold time will not be violated. An additional 5nS is picked up

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