Lexicon RV-8, Service Manual

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Lexicon
The user port is implemented by PA3_RXD1 (48) and PA4_TXD1 (47). Connecting an HDI emulated
hyperterminal to this port allows access to the system software at the code level. This port is also used to
download new code to the FLASH device.
Serial Port Settings
Each serial port must be set to the following protocols in order to work properly with hyperterminal
connections:
•
19200 Bits Per Second
•
8 Bits
•
Odd Parity
•
1 Stop Bit
•
Flow Control set to None
Interrupts
Signals: BROWN_OUT, CPU_CRYIRQ/, CPU_DSPABIRQ/, CPU_KYBDIRQ/, CPU_VIDTUNIRQ/
The CPU has provisions for six interrupt sources, of which five are used. The highest priority interrupt is
the Non-Maskable Interrupt NMI
(76). This interrupt monitors the status of the amplifier power supply. If
the voltage rails should drop by more than 10%, as would happen during brown out conditions, the
interrupt is triggered, and the unit goes into standby mode. This is the BROWN_OUT interrupt. Ferrite
bead FB14 suppresses spurious signals that may falsely trigger an NMI.
The next level of interrupt is implemented within the IRQ0 (49) domain. This interrupt is dedicated to
monitoring the status for the front panel pushbutton array. An interrupt is generated when the button is
pressed, and a second one when it is released. This is CPU_KYBDIRQ/.
IRQ1 (46) is currently unused. It may be used as an interrupt source monitor or a general purpose I/O in
the future.
IRQ2 (43) monitors the status of the SPI port transfers to and from the algorithm DSPs. Currently this
interrupt is masked off by the system software, but it remains as a provision. This is CPU_DSPABIRQ/.
IRQ3 (42) monitors the status of INTREQ or’ed with FINTREQ from the output steering DSP (U25). Each
indicates out-going data from the DSP sub-modules within this chip that must be read by the host
processor. This is CPU_CRYIRQ/.
IRQ[4:5] are internal interrupts. They are not utilized outside of the CPU.
IRQ6 (31) is a shared resource with the CPU address bit 20. As such, it is not available for use.
IRQ7 (32) monitors interrupts from the Video Board and from the Tuner Module. This is
CPU_VIDTUNIRQ/.
FPGA Configuration
Signals: FPGA_INIT/, FPGA_PROG/, FPGA_DONE, FPGA_SDATA, FPGA_CCLK
The FPGA is programmed during the boot phase. This is accomplished by serially loading the device with
the appropriate code. The process begins when the CPU asserts FPGA_PROG/ low on port
PE6 (104).
In response, the FPGA asserts FPGA_INIT/ low; the CPU monitors PE5 (102) for status of this signal.
The configuration memory inside the FPGA is automatically cleared. Once this is done, the FPGA asserts
FPGA_INIT/ high. Once the CPU receives this response, the loading of configuration data begins.
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