Lexicon RV-8, Service Manual

Page: 96 / 248

RV-8 Service Manual
Proprietary DSP A (U16)
The Memory interface and control block for U16 is shown on this page. The on-chip memory controller
provides all the necessary interface to the SDRAM. The DSP accesses the memory data bus 32-bits at
one time, eliminating the more conventional four data mask controls. These have been replaced by one
control signal
DQM (P13) which acts like an output enable during read accesses. This device also allows
for four banks of memory and provides four chip select signals. As this application uses only one memory
device,
MS0/ (N6) is the only chip select used. The WR/ (M9), RD/ (R8), BRST (N9), and ACK (M12) pins
are valid only in topologies where there is a bus master and a bus slave. As there is no host connection to
the DSPs through the Address and Data busses, and both DSPs are independent of each other, these
signals serve no function. They are connected to their analogous pins on DSP B and are pulled up by
internal resistors.
Boot Mode Configuration
The ADSP21161N supports a multitude of boot-up options. These options are chosen by hardwiring the
EBOOT (A5), LBOOT (A6), and BMS/ (A3) pins to the appropriate values. This application utilizes the
SPI boot option, therefore these pins are hardwired to a value of 010 via RP4 and R69-R71.
Proprietary Algorithm DSP B SDRAM and Flash (Sheet 5)
This sheet shows the interconnection between DSP B and its SDRAM. It also illustrates the boot
configuration for DSP B. The functionality of this page is identical to that of Sheet 4. Further discussion
would be redundant.
DSP SPI Serial and Link Ports (Sheet 6)
This sheet shows the interconnection between DSP A and DSP B, as well as the SPI host interface as
well as the audio data path into and out of the SHARCs.
SPI Interface
Signals: DSPASEL/, DSPASPICLK, DSPARXD, DSPATXD, DSPBSEL/
SPI is a serial interface protocol consisting of a four-wire interface: a chip select, two data pins, and a
clock pin. This interface runs in full duplex mode allowing the SHARC to simultaneously receive and
transmit data on the same port. The SHARCs are configured as slave devices to a master boot device.
The interface between the CPU and the SPI port on each SHARC is implemented in the FPGA. The
receive and transmit wires as well as the SPI clock are shared between the two DSPs, while selection of
the devices is accomplished with their individual chip select signals.
The SPI interface is essentially a shift register that serially transmits and receives data synchronously with
DSPASPICLK . When a SPI transfer occurs, data is shifted out of one end of the shift register on
DSPATXD and into the other end of the shift register on DSPARXD . SPI transfers to U16 are
accomplished by asserting DSPASEL/ and beginning the transfer. SPI transfers to U34 are accomplished
by asserting DSPBSEL/ and beginning the transfer. The internal registers of the SHARCs are accessed
sequentially with each transfer of a data byte.
6-20