7
TABLE OF CONTENTS
General Information
Purpose
9
Unpacking and Inspection
9
Warranty
9
Product Assistance
9
Maintenance Agreements
9
Documentation Discrepancies
10
Software Licensing Agreement
10
Service Procedure
10
Front-Panel Diagram
11
1. Product Description
1.1
General
13
1.2
Specifications
13
1.3
Analog Inputs
14
1.4
Clear Function
14
1.5
External Gate Input (GATE)
15
1.6
ADC Pedestals
15
1.7
Test Function
15
1.8
Pedestal Memory
16
1.9
Status Register
16
1.10 ECL Port Output
18
1.11 ECL Port Readout Handshake
19
1.12 Halt of Readout on the ECL Port
20
1.13 CAMAC Readout
20
1.14 LAM Handling
21
1.15 FERA System Connections
21
1.16 Packaging and Power Requirements
22
2.0
Operating Instructions
2.1
General
31
2.2
CLEAR and GATE Functions
32
2.3
Charge to Time Converters
32
2.4
Test Circuit
33
2.5
Digital Interpolators
33
2.6
Real Time Counters
33
2.7
Clock Generators
34
2.8
Pedestal Memory
34
2.9
Data Compression and Readout Logic
34
2.10 ECL Port Readout Circuit
36
2.11 CAMAC Readout Circuit
36
2.12 CAMAC Functions Decoder
36
2.13 ADC Resolution Adjustment
36
3.0 List of Figures and Tables
1.1
Readout Timing Diagram
23
1.2
ECL Port Timing Diagram
24
1.3
FERA System Connections
25
1.4
Model 4301 FERA Driver Block Diagram
26
1.5
Localization of Removable Resistors & VGND-GND Jumper
27
1,1a Table: Status Register Format
28
Summary of Contents for 4300B
Page 22: ...25 Figure 1 3 FERA SYSTEM CONNECTIONS ...
Page 23: ...26 Figure 1 4 MODEL 4301 FERA DRIVER BLOCK DIAGRAM ...
Page 24: ...27 Figure 1 5 LOCALIZATION OF REMOVABLE RESISTORS AND VGND GND JUMPER ...
Page 34: ...38 Figure 2 1 MODEL 4300B BLOCK DIAGRAM ...
Page 35: ...39 Figure 2 2 CHARGE TO TIME CONVERTER BLOCK DIAGRAM AND TIMING ...
Page 36: ...40 Figure 2 3 TIME TO DIGITAL CONVERTER BLOCK DIAGRAM AND TIMING ...