18
CCE = 1:
Enables the data compression cycle after an
ECL readout or conversation, for sequential CAMAC readout
mode only. This procedure takes 2.5
µ
s and all data < 1
count are eliminated. If no data are valid, the CAMAC
sequential readout will not be initiated. The Header Word
and the data are structured in the same way as for ECL port
readout.
CSR:
CAMAC Sequential Readout (W14, R14).
CSR = 0:
Enables CAMAC random access readout. Data
compression is blocked (CCE indifferent). The 16 ADC data,
with or without pedestal subtraction, may be read without
their subaddresses with the function F(2). Subaddress A
determines the channel to be read (A(0) = channel 0, etc.).
The Q response to this function is given when CAMAC
readout is initialized and as long as no clear function has
been applied.
CSR = 1:
Enables the procedure for sequential CAMAC
readout. Valid data may be read sequentially with the
function F(2) A.(0) to A(15); (subaddress A is not decoded).
At the end of S2, the following data word is accessed. A Q
response is given for each valid data word until the last data
word (Q stop mode). If after compression no valid data are to
be read, the Q response is inhibited.
CLE:
CAMAC Look-at-me Enable (W15,R15).
CLE = 0:
LAM output is inhibited.
CLE = 1:
Results in the setting of LAM as soon as data are
ready to be read by CAMAC. In the case of compressed
sequential readout where there are no valid data, the LAM
will not be set.
OAFS:
Overflow Suppress (W16, R16).
This bit sits as the ECE or the CCE bits but operating both on the zeros
and the overflows. That is when OFS = 1 not only zeros (< 1) but also
overflows will be suppressed. In particular, when ECE = 1 the suppres-
sion will be performed on the CAMAC readout. This procedure takes
again 2.5
µ
s as in the case of zero suppression alone.
Note:
The CAMAC initialization command Z sets the Model 4300B
Status Register for the ECL port readout to be followed by CAMAC
sequential readout with transmission of the LAM. Both readouts will have
pedestal subtraction and data compression. (See Readout Timing
Diagram Figure 1.1).
1.10 ECL Port Output
The ECL port output delivers 16-bit data words at complementary ECL
levels. The maximum output frequency is 10 MHz. If the user wishes to
connect this output to a bus on which other outputs are already con-
nected, the pull-down resistors must be removed from the module (see
Figure 1.5). When lit, the LED indicator (PD. ON), located over the ECL
port connector, indicates that these resistors are mounted. When several
Summary of Contents for 4300B
Page 22: ...25 Figure 1 3 FERA SYSTEM CONNECTIONS ...
Page 23: ...26 Figure 1 4 MODEL 4301 FERA DRIVER BLOCK DIAGRAM ...
Page 24: ...27 Figure 1 5 LOCALIZATION OF REMOVABLE RESISTORS AND VGND GND JUMPER ...
Page 34: ...38 Figure 2 1 MODEL 4300B BLOCK DIAGRAM ...
Page 35: ...39 Figure 2 2 CHARGE TO TIME CONVERTER BLOCK DIAGRAM AND TIMING ...
Page 36: ...40 Figure 2 3 TIME TO DIGITAL CONVERTER BLOCK DIAGRAM AND TIMING ...
