19
modules are connected on the ECL port bus, only the positive ECL
outputs are used, the negative ECL outputs may be connected to ground
to improve shielding. See Table 1.1.b
for data format.
1.11 ECL Port Readout
Handshake
In order to provide for the synchronization of the ECLbus, the following
signals are utilized. These signals, transmitted via front-panel command
connectors, are described below:
a.
REQ (REQuest output) is activated as soon as data to be read by
the ECL port are ready and remains until the last data has been read
(or a clear function has been given).
b.
REN (Readout ENable input) enables the ECL port output if REQ
signal is present, or the PASS output if the REQ signal is released.
The REN signal must be maintained throughout the entire ECL port
readout. The REN input is automatically considered as active if it is
not connected.
c.
PASS (PASS output) is enabled by the REN input if the REQ signal
is not present. This signal indicates that the ECL port readout is
complete, or that there is nothing to be read in the module.
d.
WST (Write STrobe output) indicates that a data word is present on
the ECL port output. WST is given a minimum of 10 ns after the data
and its minimum duration is 40 ns.
e.
WAK (Write acknowledge input) indicates that the data on the ECL
port has been accepted. The module with control of the ECLbus
releases WST and passes on to next data word. WAK can be
released after WST is cleared and its duration must be a minimum of
30 ns.
The ECL port control signal sequence is as follows (see ECL port Timing
Diagram, Figure 1.2): When data are ready, the REQ is generated and
inhibits the PASS output. Once REN is received, the first data word is
sent to the ECL port output and the WST is activated. This state remains
unchanged until a WAK signal is applied; this allows the readout to be
delayed if necessary. As soon as the WAK is received, the WST is
released, but an internal protection keeps the WST duration from being
less than 40 ns. The trailing edge of the WST loads the next data word
on the ECL port. In order to permit the delay of the readout, WS is
reactivated after approximately 50 ns.
When the WAK is received after the last data word has been read, the
REQ signal is disabled and the REN signal is routed to the PASS output,
indicating that the readout is complete and enabling the readout of the
next 4300B module.
The Model 4300B is designed to allow direct connection of WST on WAK
and thus obtain data on the ECL port at a frequency of approximately
10 MHz.
After a Z command, the ECL port readout is automatically enabled along
with pedestal subtraction and data compression.
Summary of Contents for 4300B
Page 22: ...25 Figure 1 3 FERA SYSTEM CONNECTIONS ...
Page 23: ...26 Figure 1 4 MODEL 4301 FERA DRIVER BLOCK DIAGRAM ...
Page 24: ...27 Figure 1 5 LOCALIZATION OF REMOVABLE RESISTORS AND VGND GND JUMPER ...
Page 34: ...38 Figure 2 1 MODEL 4300B BLOCK DIAGRAM ...
Page 35: ...39 Figure 2 2 CHARGE TO TIME CONVERTER BLOCK DIAGRAM AND TIMING ...
Page 36: ...40 Figure 2 3 TIME TO DIGITAL CONVERTER BLOCK DIAGRAM AND TIMING ...
