23
T3:
Depends on the ECE status, data values and ECL port readout rate
(> 100 nsec per word).
ECE = 0 : T3 = 16 (> 100 nsec per word);
ECE = 1 and all or part of the data = 0 : T3 = 2 to 17
(> 100 nsec per word);
ECE = 1 and all data = 0 : T3 = 0 and the ECL port readout is
suppressed.
T4:
Depends on the CSR and CCE status.
CSR = 0 or (CSR = 1 and CCE = 0) : T4 = 0
(CSR = 1 and CCE = 1) : T4 = 2.3
µ
sec.
T5:
Depends on the CCE status, data values and CAMAC
readout rate (> 1
µ
sec per word).
CCE = 0 : T5 = 16 (> 1
µ
sec per word).
CCE = 1 and all or part of the data = 0 : T3 = 2 to 17
(1
µ
sec per word).
CCE = 1 and all data = 0 : the CAMAC sequential readout and LAM
are suppressed.
Figure 1.1: READOUT TIMING DIAGRAM
Note: This diagram does not define the logic states, low = OFF and high = ON.
Summary of Contents for 4300B
Page 22: ...25 Figure 1 3 FERA SYSTEM CONNECTIONS ...
Page 23: ...26 Figure 1 4 MODEL 4301 FERA DRIVER BLOCK DIAGRAM ...
Page 24: ...27 Figure 1 5 LOCALIZATION OF REMOVABLE RESISTORS AND VGND GND JUMPER ...
Page 34: ...38 Figure 2 1 MODEL 4300B BLOCK DIAGRAM ...
Page 35: ...39 Figure 2 2 CHARGE TO TIME CONVERTER BLOCK DIAGRAM AND TIMING ...
Page 36: ...40 Figure 2 3 TIME TO DIGITAL CONVERTER BLOCK DIAGRAM AND TIMING ...
