32
The adjustable FS (Full Scale) monostable enables the clock generator
(Gray code) and the real time scale memorization latches. The end of
this monostable signal clears the CLEAR flip-flop of the charge-to-time
converters and triggers the readout circuit.
The duration of the FS monostable is adjusted (via the FS potentiometer)
to produce a number of clocks slightly larger than the number of clocks
necessary for the digitization of the Full Scale. Its length depends on the
ADC resolutions (see Section 2.13). The CAMAC command I, integrated
by 100 nsec, inhibits the GATE input.
2.3 Charge-to-Time
Converters
The charge-to-time conversion is provided for each channel by a mono-
lithic integrated circuit, LeCroy Model MQT200F. This circuit is based on
the dual ramp Wilkinson principle and the integration of the charge by a
capacitor. This capacitor is charged during the entire duration of the
GATE by the input current and discharged by a constant current after the
closing of the GATE. The time conversion is determined by the duration
of the discharge which is proportional to the amplitude of the charge
injected on the capacitor.
The following description refers to Figure 2.2. The MQT200F analog
input impedance is approximately 0 ohm and its potential is equal to that
of the common ground VGND. A terminating resistor of 50 ohm (or
100 ohm), mounted in series with this input, converts the input voltage to
an input current (
i
in). In the quiescent state, a switch shunts the inputs of
the output comparator. Time output is thus at the zero logic state.
When a GATE is applied, the input current iin is switched on to the
integrating capacitor, the output comparator MOSFET is switched off and
the pedestal injection circuit is activated. The charge current of the CI
integration capacitor is thus equal to:
I
C
= i
IN
+ i
P
- I
RU
+ I
PC
i
IN
is the input current.
i
P
is the current generated by the discharge of Cp, the capacitor of
the pedestal injection circuit.
I
RU
is the constant discharge of the integration capacitor.
I
PC
is the constant current permitting compensation of IRU and all
leakage currents to reduce the pedestal dependence on the GATE
width.
Time output is turned ON.
On the trailing edge of GATE, the input charge currents i
IN
are switched
back to the +15 V power supply and only the constant current I
RU
dis-
charges the integration capacitor. The MOSFET shunts on the inputs of
the output comparator is switched on again at the end of the conversion
(FS monostable). The time output is turned OFF when the integration
capacitor voltage level reaches the output comparator reference voltage
value; its duration is proportional to the gated input charge.
Summary of Contents for 4300B
Page 22: ...25 Figure 1 3 FERA SYSTEM CONNECTIONS ...
Page 23: ...26 Figure 1 4 MODEL 4301 FERA DRIVER BLOCK DIAGRAM ...
Page 24: ...27 Figure 1 5 LOCALIZATION OF REMOVABLE RESISTORS AND VGND GND JUMPER ...
Page 34: ...38 Figure 2 1 MODEL 4300B BLOCK DIAGRAM ...
Page 35: ...39 Figure 2 2 CHARGE TO TIME CONVERTER BLOCK DIAGRAM AND TIMING ...
Page 36: ...40 Figure 2 3 TIME TO DIGITAL CONVERTER BLOCK DIAGRAM AND TIMING ...
