22
The Model 4301 FERA Driver is designed to receive and distribute all
signals necessary for system functioning. It serves as an intermediary
between the external logic and the 4300B modules for the following
signals and commands:
a.
Via Command bus
- Distributes the CLEAR received on the front-panel or by a CAMAC
command.
- Distributes the GATE received on the front-panel.
- Delivers the CAMAC programmable TRV for the test.
- Receives the REQ signals from the 4300B modules and, after an
adjustable delay covering the dispersion of these REQ signals,
generates RQO and REO signals. RQO represents the logic OR of
all REQ signals on the bus. REO is in addition gated by IRI.
- Regenerates on the front-panel the WST signal received from the
4300B modules.
- Distributes to the 4300B modules the response signal WAK
received from the front-panel.
b.
Via the ECL port bus
- Receives and translates single-ended ECL level data from the
4300B modules and converts them to ECL complementary levels
for the front-panel data output connector.
c.
Via Enable/pass readout bus.
- Generates the ECL port readout signal, REN, received from the
front-panel.
See Figure 1.4, Model 4301 FERA Driver Block Diagram.
1.16 Packaging and
Power Requirements
The Model 4300B FERA is packaged in a standard # 1 CAMAC module.
It dissipates a total of 30 watts with the following current distribution:
< 0.1 A at +24 V
< 2.1 A at
+6 V
< 2.7 A at
-6 V
The current at +24 V depends on the current of the 16 analog inputs. It is
equal to 65 mA plus the mean of the sum of all input currents.
Note:
When all output pull-down and input matching resistors are
removed, the current at -6 V is reduced to 2.4 A.
4300B Status
T1:
Depends on the resolution. 8 bits = 1.8 use; 9 bits = 2.9
µ
sec;
10 bits = 4.8
µ
sec; 11 bits = 8.5
µ
sec.
T2:
Depends on the ECE status.
ECE = 0 : T2 = 0
ECE = 1 : T2 = 2.3
µ
sec
Summary of Contents for 4300B
Page 22: ...25 Figure 1 3 FERA SYSTEM CONNECTIONS ...
Page 23: ...26 Figure 1 4 MODEL 4301 FERA DRIVER BLOCK DIAGRAM ...
Page 24: ...27 Figure 1 5 LOCALIZATION OF REMOVABLE RESISTORS AND VGND GND JUMPER ...
Page 34: ...38 Figure 2 1 MODEL 4300B BLOCK DIAGRAM ...
Page 35: ...39 Figure 2 2 CHARGE TO TIME CONVERTER BLOCK DIAGRAM AND TIMING ...
Page 36: ...40 Figure 2 3 TIME TO DIGITAL CONVERTER BLOCK DIAGRAM AND TIMING ...
