34
2.7 Clock Generator
The reference clocks are generated by a voltage controlled oscillator
controlled by an LC tank. Its oscillation frequency is adjusted to 125 MHz
by means of the variable F capacitor. This frequency is divided by the
gray code generator for the interpolator command.
The following description refers to Figure 2.3
.
To synchronize its phase,
the 125 MHz oscillator is stopped for 400 nsec by a monostable triggered
at the end of the GATE signal. Simultaneously, the gray code clear is
released and remains so until the FS monostable resets.
The gray code generator consists of a group of four flip-flops dividing the
125 MHz oscillator frequency into four clocks of 31.25 MHz. These four
clocks are separated from each other by 4 nsec to form the gray code
and are distributed, via drivers, on two 4-line busses for the odd and
even channel interpolators. The resistor terminations of these busses are
polarized by a power supply (-2 V). It is adjustable by means of the
-2 V potentiometer. This power supply influences the differential linearity
and the clock output levels of the interpolators. It is adjusted between
-1.8 V and -2 V for accurate operation.
2.8 Pedestal Memory
The pedestal memory consists of two 16 x 4 bit memories. When the
Model 4300B is in “ready” state, their select inputs are enabled. They
may be loaded by the CAMAC function F(17).S1) or read by F(1)S2. The
subaddress A(0 to 15) are applied to the internal address bus via a
multiplexer. During readout, the drivers on lines R9 to R16 are disabled.
When the module is in the “busy” state, the memory outputs are enabled
only if the pedestal subtraction is programmed. In the case where the
memory outputs are disabled, zero subtraction is guaranteed by the pull-
up resistors.
2.9 Data Compression
and Readout Logic
During readout, the readout logic addresses one of the ADC channels
and its corresponding pedestal in the Pedestal Memory. The 11 bits of
this ADC data and its pedestal are applied to the subtractor inputs. The
11 bits resulting from the subtraction are loaded into the Data Memory
register. The output of the zero detection, (performed by a diode AND
function is reintroduced into subtractor to disable the Carry output for
values equal to or smaller than zero. It also sets the flip-flop clear of the
Data Memory.
The overflow command, selected on bits 2
7
to 2
10
by means of jumpers A,
B, C and D to match the ADC resolutions, sets the flip-flop which dis-
ables the Data Memory outputs and the overflow state (2047) is assured
by pull-up resistors. The position of the jumpers are as follows:
8 bit resolution
B only
(256)
9 bit resolution
C only
(516)
10 bit resolution
D only
(1024)
11 bit resolution
A,B,C,D
(1920)
Summary of Contents for 4300B
Page 22: ...25 Figure 1 3 FERA SYSTEM CONNECTIONS ...
Page 23: ...26 Figure 1 4 MODEL 4301 FERA DRIVER BLOCK DIAGRAM ...
Page 24: ...27 Figure 1 5 LOCALIZATION OF REMOVABLE RESISTORS AND VGND GND JUMPER ...
Page 34: ...38 Figure 2 1 MODEL 4300B BLOCK DIAGRAM ...
Page 35: ...39 Figure 2 2 CHARGE TO TIME CONVERTER BLOCK DIAGRAM AND TIMING ...
Page 36: ...40 Figure 2 3 TIME TO DIGITAL CONVERTER BLOCK DIAGRAM AND TIMING ...
