LeCroy 4300B, Operator'S Manual, Page: 31 / 38

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The command bits of the Status Register determine the operation mode
of the readout logic. If the module is in the “ready” state, the Status
register may be loaded with the function F(16) A(0).S1 or read with F.(0)
A(0). The function Z.S2 clears the Status Register, setting the command
bits in their true state. Two flip-flops control the readout sequence:
The first flip-flop, enabled by the end of a conversion (reset of FS
monostable), activates the ECL port readout procedure if the bit EEN is
ON.
The second flip-flop is enabled by the end of an ECL port readout, or by
the end of a conversion if the bit EEN is OFF. It activates the CAMAC
readout procedure and commands the selection of bits EPS and ECE or
CPS and CCE for the operation mode of the readout logic. These two
flip-flops are cleared by the end of CAMAC readout or by a CLEAR
command.
A start-stop oscillator (RF), adjusted to 7 MHz by means of the variable
RF adjustment, provides the clocks for the readout logic. This readout
logic operates in two different modes for either ECL port or CAMAC
readout.
a. Data compression is disabled (ECL port: EEN = ON with ECE = OFF,
CAMAC: CSR = ON with CCE = OFF, the special case where CSR =
OFF is considered as identical to data compression disabled.
Channel addresses are generated by the Address Scaler and
demultiplexer. The RF oscillator delivers two clock pulses. The first
pulse initializes the Address Scaler at address zero. The second
pulse loads the data from channel zero in the Data Memory,
increments the Address Scaler and starts the external readout via
the RE flip-flop.
b. Data compression enabled (ECL port: EEN + ON with ECE = ON,
CAMAC: CSR = ON with CCE = ON ).
A 16 channel readout cycle, addressed by the Address Scaler, is
executed. The Word Count Scaler counts the number of valid data
and addresses the Address Memory. The addresses of the valid
channels are loaded in this memory.
The RF oscillator delivers 18 clock pules. The first pulse initializes the
Address Scaler and the Word Count Scaler. The 16 following pulses
increment the Address Scaler and load the Address Memory with the
address of valid channels. The Word Count Scaler is incremented and
the RE flip-flop set only if the Carry output of the subtractor is enabled.
The last pulse decrements the Word Count Scaler, commutes the
channel addressing to the Address Memory output, and enables the
external readout with the Header Word as the first data word (or the end
of readout if no valid data present).
The RE, external Readout Enable, command is delivered either on the
ECL port readout circuit by the command ER, or on the CAMAC function
decoder and the LAM circuit by the command CR.