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LeCroy 4300B, Operator'S Manual, Page: 9 / 38

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LeCroy 4300B Operator'S Manual Download Page 9

11

MODEL 4300B

FRONT-PANEL

Pull Down ON (LED
indicator) indicates
that pull down and
input resistors are
mounted on Command
bus (Sec. 1.15)

Command Bus

Analog Inputs
(Sec 1.3)

Not connected
Write Strobe (Sec. 1.11)
Readout Request (Sec. 1.11)
Clear (Sec. 1.4)
Gate (Sec. 1.5)
Write Acknowledge (Sec. 1.11)
Ground
Test Reference Voltage (Sec. 1.7)
Readout Enable (Sec. 1.11)
Readout Enable PASS (Sec. 1.11)

Common Virtual Ground
(Sec. 1.3)

Ground (Sec 1.3)

Pull Down on (LED
Indicator) indicates
that pull down
resistors are mounted
on the ECL output
Port (Sec. 1.15)

ECL output port
(Sec 1.10)

Last 2 pins not
connected

Summary of Contents for 4300B

Page 1: ...1 OPERATOR S MANUAL MODEL 4300B CAMAC 16 CHANNEL FAST ENCODING READOUT ADC FERA Revised March 1998 ECO 1007 ...

Page 2: ...99 Tel 914 578 6013 Fax 914 578 5984 E mail lrs_sales lecroy com lrs_support lecroy com Copyright March 1998 LeCroy is a registered trademark of LeCroy Corporation All rights reserved Information in this publication supersedes all earlier versions Innovators in Instrumentation ...

Page 3: ...ty of the end user acting as the system integrator to ensure that the overall system is CE compliant This product was demonstrated to meet CE conformity using a CE compliant crate housed in an EMI RFI shielded enclosure It is strongly recommended that the system integrator establish these same conditions ...

Page 4: ...should be turned off during insertion and removal of unit to avoid possible damage caused by momentary misalignment of contacts See pocket in back of manual for schematics parts list and additional addenda with any changes to manual ...

Page 5: ...MAC Readout 20 1 14 LAM Handling 21 1 15 FERA System Connections 21 1 16 Packaging and Power Requirements 22 2 0 Operating Instructions 2 1 General 31 2 2 CLEAR and GATE Functions 32 2 3 Charge to Time Converters 32 2 4 Test Circuit 33 2 5 Digital Interpolators 33 2 6 Real Time Counters 33 2 7 Clock Generators 34 2 8 Pedestal Memory 34 2 9 Data Compression and Readout Logic 34 2 10 ECL Port Readou...

Page 6: ...mat 29 2 1 Model 4300B Block Diagram 38 2 2 Charge to Time Converter Block Diagram 39 2 3 Time to Digital Converter Blcok Diagram and Timing 40 4 0 Appendix 4 1 ECL Differntial I O Levels 41 4 2 ECL Single Ended I O Levels 42 ...

Page 7: ...ed to the Customer Service Department or an authorized service facility within the warranty period provided that the warrantor s examination discloses that the product is defective due to workmanship or materials and has not been caused by misuse neglect accident or abnormal conditions or operations The purchaser is responsible for the transportation and insurance charges arising from the return o...

Page 8: ...m for your use on a single machine Transfer the software and the license to another party if the other party accepts the terms of this agreement and you relinquish all copies whether in printed or machine readable form including all modified or merged versions SERVICE PROCEDURE Products requiring maintenance should be returned to the Customer Service Department or authorized service facility If un...

Page 9: ...e Strobe Sec 1 11 Readout Request Sec 1 11 Clear Sec 1 4 Gate Sec 1 5 Write Acknowledge Sec 1 11 Ground Test Reference Voltage Sec 1 7 Readout Enable Sec 1 11 Readout Enable PASS Sec 1 11 Common Virtual Ground Sec 1 3 Ground Sec 1 3 Pull Down on LED Indicator indicates that pull down resistors are mounted on the ECL output Port Sec 1 15 ECL output port Sec 1 10 Last 2 pins not connected ...

Page 10: ...alues Both the Status Register and Pedestal Memory must be previously loaded via CAMAC Data may be read out either via the CAMAC dataway or the ECL port The state of the Status Register determines the readout modes The ECL port output located on the front panel is first activated and delivers ADC data sequentially in words of 16 bits 8 to 11 bits of data plus 4 subaddress at differential ECL level...

Page 11: ... be applied to the 4300B unit see Figure 1 1 1 3 Analog Inputs The 16 analog inputs are designed for negative signals with respect to a floating common signal ground Common Virtual Ground which is coupled to the module ground via capacitors Input impedance is 50 or 100 ohm with respect to the Common Virtual Ground All 16 inputs are protected against positive signals by diodes connected to the modu...

Page 12: ...DC Pedestals The 16 ADC pedestals are generated by the injection of a small charge at the leading edge of the GATE The pedestal value may be adjusted via an internal potentiometer 0 adjustment A common circuit compensates to a large degree the variations of the pedestals with respect to GATE width The Model 4300B is adjusted so that the pedestals remain between 1 and 13 pC for GATE durations of 50...

Page 13: ...formed with F 1 and the same subaddresses A 0 to A 15 The 8 bits to be read out are sent on lines R1 to R8 F 17 A 0 to A 15 and F 1 A 0 to A 15 are possible only when the module is in the ready state there is no Q response if they cannot be accepted 1 9 Status Register The Status Register is composed of two distinct sections See Table 1 1 a The low order 8 bit Virtual Station Number VSN determines...

Page 14: ...c If there are no valid data ECL port readout will not take place and CAMAC readout will automatically be enabled In order to determine the origin of data a Header Word is sent as the first word and the channel subaddress is included in the ADC data word The Header Word is identified by the 16th bit which always 1 and is composed of 8 VSN Virtual Station Number Status Register bits and 4 WC Word C...

Page 15: ...nse is inhibited CLE CAMAC Look at me Enable W15 R15 CLE 0 LAM output is inhibited CLE 1 Results in the setting of LAM as soon as data are ready to be read by CAMAC In the case of compressed sequential readout where there are no valid data the LAM will not be set OAFS Overflow Suppress W16 R16 This bit sits as the ECE or the CCE bits but operating both on the zeros and the overflows That is when O...

Page 16: ...e WAK Write acknowledge input indicates that the data on the ECL port has been accepted The module with control of the ECLbus releases WST and passes on to next data word WAK can be released after WST is cleared and its duration must be a minimum of 30 ns The ECL port control signal sequence is as follows see ECL port Timing Diagram Figure 1 2 When data are ready the REQ is generated and inhibits ...

Page 17: ... random access readout The channel addressed for readout is selected by the subaddress A The Q response to the readout function is delivered once the data are available as long as a clear function has not yet been applied Data compression is suppressed and all 16 data words may be read Pedestal subtraction commanded by CPS may be carried out or not The data are transferred on lines R1 to R11 witho...

Page 18: ...4300B modules controlled by the Model 4301 FERA Driver see Figure 1 3 and Model 4301 User s Manual This driver sends or receives all the signals necessary to operate the system The following interconnections must be made to ensure proper operation of the system a Command Bus between Model 4301 and each Model 4300B 8 x 2 wire flat cable b ECL port data Bus between INput connector of Model 4301 and ...

Page 19: ...K received from the front panel b Via the ECL port bus Receives and translates single ended ECL level data from the 4300B modules and converts them to ECL complementary levels for the front panel data output connector c Via Enable pass readout bus Generates the ECL port readout signal REN received from the front panel See Figure 1 4 Model 4301 FERA Driver Block Diagram 1 16 Packaging and Power Req...

Page 20: ...ed T4 Depends on the CSR and CCE status CSR 0 or CSR 1 and CCE 0 T4 0 CSR 1 and CCE 1 T4 2 3 µsec T5 Depends on the CCE status data values and CAMAC readout rate 1 µsec per word CCE 0 T5 16 1 µsec per word CCE 1 and all or part of the data 0 T3 2 to 17 1 µsec per word CCE 1 and all data 0 the CAMAC sequential readout and LAM are suppressed Figure 1 1 READOUT TIMING DIAGRAM Note This diagram does n...

Page 21: ...24 Figure 1 2 ECL PORT TIMING DIAGRAM All times in nsec typical Note This diagram does not define the logic state of the signals low OFF and high ON ...

Page 22: ...25 Figure 1 3 FERA SYSTEM CONNECTIONS ...

Page 23: ...26 Figure 1 4 MODEL 4301 FERA DRIVER BLOCK DIAGRAM ...

Page 24: ...27 Figure 1 5 LOCALIZATION OF REMOVABLE RESISTORS AND VGND GND JUMPER ...

Page 25: ...28 Loaded by F 16 A 0 Read by F 0 A 0 Table 1 1 a STATUS REGISTER FORMAT W16 R16 W15 R15 W14 R14 W13 R13 W12 R12 W11 R11 W10 R10 W9 R9 W8 R8 W1 R 1 OFS CLE CSR CCE CPS EEN ECE EPS VSN ...

Page 26: ... 2047 10 bit resolution 0 to 1023 overflow 2047 11 bit resolution 0 to 1919 overflow 2047 SA Channel Subaddress DATA DATA R16 R11 R1 HEADER WORD LAST CHANNEL 2 to 17 words DATA DATA DATA 1 0 0 0 0 0 WC 0 to 15 FIRST SA SA SA SA LAST SA 0 0 0 VSN R8 FIRST CHANNEL CHANNELS WITH DATA 0 ECL port readout EEN 1 ECE 0 OFS X CAMAC readout CSR 1 CCE 0 OFS 0 DATA 8 bit resolution 0 to 255 overflow 2047 9 bi...

Page 27: ...t be modified without adequate control 2 2 CLEAR and GATE Functions The state of the BUSY flip flop determines the two module states ready and busy It is cleared ready state and remains at zero throughout the duration of a CLEAR function This CLEAR function is generated by the front panel CLEAR input or the CAMAC decoder Z S2 C S2 F 9 A 0 S2 This function also clears and maintains the CLEAR flip f...

Page 28: ...ximately 0 ohm and its potential is equal to that of the common ground VGND A terminating resistor of 50 ohm or 100 ohm mounted in series with this input converts the input voltage to an input current i in In the quiescent state a switch shunts the inputs of the output comparator Time output is thus at the zero logic state When a GATE is applied the input current iin is switched on to the integrat...

Page 29: ...rate the time to digital conversion digital interpolators are used between the time output of the MQT200Fs and the real time counters The following description refers to Figure 2 3 Each interpolator is made of four latches controlled by four clock signals at 4 nsec inter vals Looking at the different consecutive states of these four clock signals it can be seen that the time function of the four s...

Page 30: ... When the Model 4300B is in ready state their select inputs are enabled They may be loaded by the CAMAC function F 17 S1 or read by F 1 S2 The subaddress A 0 to 15 are applied to the internal address bus via a multiplexer During readout the drivers on lines R9 to R16 are disabled When the module is in the busy state the memory outputs are enabled only if the pedestal subtraction is programmed In t...

Page 31: ...ression disabled Channel addresses are generated by the Address Scaler and demultiplexer The RF oscillator delivers two clock pulses The first pulse initializes the Address Scaler at address zero The second pulse loads the data from channel zero in the Data Memory increments the Address Scaler and starts the external readout via the RE flip flop b Data compression enabled ECL port EEN ON with ECE ...

Page 32: ...e state of the command CCE The trailing edge of the function F 2 S2 loads the subsequent data into the Data Memory and increments the Address Scaler and Word Count Scaler After the readout of the last data detected by the zero state of the Word Counter Scaler the command CR is released and the LAM flip flop is cleared When the random access readout is programmed CSR OFF the channel addressing is c...

Page 33: ... Z or F 9 A 0 or C and F 25 A 0 measuring the output width on pin 13 of the G2 integrated circuit under the FS potentiometer 4300B FERA Resolution FS Width Jumper Position Option 8 9 bits 8 bits 1 6 µsec B 9 bits 2 6 µsec C Option 10 11 bits 10 bits 4 65 µsec D 11 bits 8 35 µsec A B C D ...

Page 34: ...38 Figure 2 1 MODEL 4300B BLOCK DIAGRAM ...

Page 35: ...39 Figure 2 2 CHARGE TO TIME CONVERTER BLOCK DIAGRAM AND TIMING ...

Page 36: ...40 Figure 2 3 TIME TO DIGITAL CONVERTER BLOCK DIAGRAM AND TIMING ...

Page 37: ...41 APPENDIX 3 1 ECL DIFFERENTIAL I O LEVELS ...

Page 38: ...42 APPENDIX 3 2 ECL SINGLE ENDED I O LEVELS ...

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