CP307
Configuration
ID 34424, Rev. 3.0
Page 4 - 15
P R E L I M I N A R Y
4.5.7
Board Interrupt Configuration Register
The Board Interrupt Configuration register holds a series of bits defining the interrupt routing
for the Watchdog. If the Watchdog Timer fails, it can generate two independent hardware
events: NMI and IRQ5 interrupt.
The enumeration signal is generated by a hot swap compatible board after insertion and prior
to removal. The system uses this interrupt signal to force software to configure the new board.
The derate signal indicates that the power supply is beginning to derate its power output.
Table 4-12: Board Interrupt Configuration Register
REGISTER NAME
BOARD INTERRUPT CONFIGURATION REGISTER
SIZE
ADDRESS
0x289
8 bits
BIT POSITION
MSB
7
6
5
4
3
2
1
0
LSB
CONTENT
Res.
CFNMI
CFIRQ
CEIRQ
CDIRQ
Res.
WIRQ1
WIRQ0
DEFAULT
0
0
0
0
0
0
0
0
ACCESS
R
R/W
R/W
R/W
R/W
R
R/W
R/W
BIT
NAME
DESCRIPTION / FUNCTION
7
Res.
Reserved
6
CFNMI
CPCI fail signal to NMI routing:
0 Disabled
1 Enabled
5
CFIRQ
CPCI fail signal to IRQ5 routing:
0 Disabled
1 Enabled
4
CEIRQ
CPCI enum signal to IRQ5 routing:
0 Disabled
1 Enabled
3
CDIRQ
CPCI derate signal to IRQ5 routing:
0 Disabled
1 Enabled
2
Res.
Reserved
1 - 0
WIRQ[1:0] Watchdog interrupt routing:
11 NMI
10 Reserved
01 IRQ5
00 Disabled
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