Configuration
CP307
Page 4 - 8
ID 34424, Rev. 3.0
P R E L I M I N A R Y
4.5
CP307-Specific Registers
The following registers are special registers which the CP307 uses to watch the onboard
hardware special features and a number of CompactPCI control signals.
Normally, only the system BIOS uses these registers, but they are documented here for
application use as required.
4.5.1
Watchdog Timer Control Register
The CP307 has one Watchdog Timer provided with a programmable timeout ranging from 125
msec to 256 sec. Failure to strobe the Watchdog Timer within a set time period results in a
system reset, NMI or an interrupt. The NMI and interrupt mode can be configured via the board
interrupt configuration register (0x289).
There are four possible modes of operation involving the Watchdog Timer:
• Timer only mode
• Reset mode
• Interrupt mode
• Dual stage mode
At power on the Watchdog is not enabled. If not required, it is not necessary to enable it. If re-
quired, the bits of the Watchdog Timer Control Register (0x282) must be set according to the
application requirements. To operate the Watchdog, the mode and time period required must
first be set and then the Watchdog enabled. Once enabled, the Watchdog can only be disabled
or the mode or the timeout changed by powering down and then up again. To prevent a Watch-
dog timeout, the Watchdog must be retriggered before timing out. This is done by writing a ’1’
to the WTR bit. In the event a Watchdog timeout does occur, the WTE bit is set to ’1’. What
transpires after this depends on the mode selected.
The four operational Watchdog Timer modes can be configured by the WMD[1:0] bits, and are
described as follows:
Timer only mode - In this mode the Watchdog is enabled using the required timeout period.
Normally, the Watchdog is retriggered by writing a ’1’ to the WTR bit. In the event a timeout
occurs, the WTE bit is set to ’1’. This bit can then be polled by the application and handled ac-
cordingly. To continue using the Watchdog, write a ’1’ to the WTE bit, and then retrigger the
Watchdog using WTR. The WTE bit retains its setting as long as no power down-up is done.
Therefore, this bit may be used to verify the status of the Watchdog.
Reset mode - This mode is used to force a hard reset in the event of a Watchdog timeout. To
be effective, the hard reset must not be masked or otherwise negated. In addition, the WTE bit
is not reset by the hard reset, which makes it available if necessary to determine the status of
the Watchdog prior to the reset.
Interrupt mode - This mode causes the generation of an interrupt in the event of a Watchdog
timeout. The interrupt handling is a function of the application. If required, the WTE bit can be
used to determine if a Watchdog timeout has occurred.
Dual stage mode - This is a complex mode where in the event of a timeout two things occur: 1)
an interrupt is generated, and 2) the Watchdog is retriggered automatically. In the event a sec-
ond timeout occurs immediately following the first timeout, a hard reset will be generated. If the
Note ...
Take care when modifying the contents of these registers as the system BIOS
may be relying on the state of the bits under its control.
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