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KPCI-PIO24 User’s Manual
Interrupts and I/O Address Mapping
4-3
Control and data register memory assignments
The KPCI-PIO24 normally operates in the target mode and uses eight consecutive memory
mapped locations at BADDR1 for its control and data ports. The base address for these locations
is automatically assigned by the Plug and Play feature upon power up. Each offset from the base
address is specified as a multiple of four bytes (modulo 4 addressing), because each offset
specifies a four byte (32 bit) wide register. Refer to Table 4-1; the prefix ‘0x’ in Table 4-1
designates hexadecimal.
NOTE
The term “Base” address in Table 4-1 does not have the same
meaning for a PCI board, such as the KPCI-PIO24, as for an ISA
board. The base address for your KPCI-PIO24 is a memory mapped
address, BADDR1, that is assigned by Plug and Play. It is not a fixed,
user assigned I/O address such as 0x300 or 0x310.
Table 4-1
Data and control register addresses
* Data Register Format, 32 Bit
MSB
LSB
The control register bit assignments for each port are listed in Table 4-2.
Address
Contents
I/O Function
Base + 0x0 offset
Port group
1
0 data
Read/Write
Base + 0x4 offset
Not used
N/A
Base + 0x8 offset
Not used
N/A
Base + 0xC offset
Not used
N/A
Base + 0x10 offset
Control register bits for
port group 0
Write only
Base + 0x14 offset
Not used
N/A
Base + 0x18 offset
Not used
N/A
Base + 0x1C offset
Not used
N/A
1
Contains a PA port, a PB port and a PC port, as in the emulated
8255 chip.
4 High
Bits of Port C
Not
Used
Not
Used
4 Low
Bits of Port C
8 Bits of
Port B
8 Bits of
Port A
*
Summary of Contents for KPCI-PIO24
Page 12: ...1 Overview...
Page 14: ...2 General Description...
Page 18: ...3 Installation...
Page 29: ...4 Interrupts and I O Address Mapping...
Page 35: ...5 Troubleshooting...
Page 38: ...5 4 Troubleshooting KPCI PIO24 User s Manual Figure 5 1 Problem isolation flowchart...
Page 56: ...A Specifications...
Page 58: ...B Glossary...