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KPCI-PIO24 User’s Manual
Troubleshooting
5-15
Figure 5-8
Correct bit patterns when port A is set to bit pattern 2.
15. Based on the observations in step 14, do the following:
•
If the bit patterns for ports A, B, and C do not all agree, the board is not functioning
properly. Stop here, and return to the step in the “General problem isolation procedure”
where you were directed to do I/O bit tests (step 17 or step 26e in the “General problem
isolation procedure”).
•
If the bit patterns for ports A, B, and C do all agree, the board is functioning properly. Stop
here, and return to the step in the “General problem isolation procedure” where you were
directed to do I/O bit tests (step 17 or 26e in the “General problem isolation procedure”).
Or, optionally, now perform the output set test, as discussed in the next section, if you
have not already done so.
Output set test
The output set test checks whether logic levels measured at all KPCI-PIO24 output pins agree
with output bit patterns set by software, using a DriverLINX graphical interface.
NOTE
This test is performed without user circuits being connected to
the outputs.
Perform the output set test as follows:
1. Ready the following equipment:
•
A digital voltmeter (DVM) or a digital multimeter (DMM) set to measure voltages, or a
logic probe capable of reading TTL logic levels.
•
A means to reliably and safely connect the DMM/DVM or logic probe input to each I/O
pin. The following alternatives are suggested:
a. A screw terminal-female connector combination, Keithley part number STC-37, that
plugs directly into the I/O connector on your board. Refer to your Keithley catalog for
more information.
b. A cable assembly and terminal accessory (refer to “Using manufactured cables and
accessories” in Section 3).
c. A female 37-pin ‘D’ connector that mates with I/O connector on your board and is wired
such that the meter or logic probe can be clipped to exposed conductors. An
appropriate connector can be purchased as Keithley part no. SFC-37.
PORT A
7 6 5 4 3 2 1 0
n
n
n
n
On
n
n
n
n
&HAA
PORT B
7 6 5 4 3 2 1 0
n
n
n
n
On
n
n
n
n
&HAA
PORT C
7 6 5 4 3 2 1 0
n
n
n
n
On
n
n
n
n
&HAA
Summary of Contents for KPCI-PIO24
Page 12: ...1 Overview...
Page 14: ...2 General Description...
Page 18: ...3 Installation...
Page 29: ...4 Interrupts and I O Address Mapping...
Page 35: ...5 Troubleshooting...
Page 38: ...5 4 Troubleshooting KPCI PIO24 User s Manual Figure 5 1 Problem isolation flowchart...
Page 56: ...A Specifications...
Page 58: ...B Glossary...