Keithley KPCI-PIO24, User Manual, Page: 23 / 66

3-6 Installation KPCI-PIO24 User’s Manual
Figure 3-1
Pin assignments for I/O connector on the KPCI-PIO24 board
Table 3-1
Pin descriptions for KPCI-PIO24 I/O connector
1
Refer to “Advanced Digital I/O Configuration” in the DriverLINX on-line help and to “Inter-
rupts” in section 4 of this manual. For additional information, search your DriverLINX manuals
for the term “latching.”
Pin No. Pin label Description
1 INTERRUPT
INPUT External interrupt, edge triggered. By default, triggered by the ris-
ing edge of a TTL signal. Can set it to be triggered by the falling
edge of a TTL signal. Refer also to “Interrupts” in section 4.
Latching of input data is available through DriverLINX
1
.
2 INTERRUPT
ENABLE External interrupt enable, active low. To enable the interrupt at pin
1, connect pin 2 to digital common (pin 11, 13, 15, 17, 19, or 21).
3 to 10 PB0 to PB7 The eight I/O bits of port B. PB0 is the least significant bit (LSB)
of port B and PB7 is the most significant bit (MSB).
11, 13,
15, 17,
19, 21 DIG COM Digital common from the PCI bus.
12 N/C No connection
14 -12 V -12 V power from the PCI bus.
16 +12 V +12 V power from the PCI bus
18, 20 +5 V +5 V power from the PCI bus.
22 to 29 PC0 to PC7 The eight I/O bits of port C. PC0 is the least significant bit (LSB)
of port C and PC7 is the most significant bit (MSB).
30 to 37 PA0 to PA7 The eight I/O bits of port A. PA0 is the least significant bit (LSB)
of port A and PA7 is the most significant bit (MSB).
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
DIG COM
+5V
PA PORT
LOWER
UPPER
PC PORT
REAR VIEW
DIG COM
+5V
DIG COM
+12V
DIG COM
-12V
DIG COM
N/C
DIG COM
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
INTERRUPT ENABLE
INTERRUPT INPUT
IBM PC
POWER
SUPPLIES
PB PORT