Keithley KPCI-PIO24, User Manual, Page: 33 / 66

KPCI-PIO24 User’s Manual Interrupts and I/O Address Mapping 4-5
Table 4-3
Data transfer mode selection
When bus mastering is not invoked:
• An interrupt is always generated on the edge of every external interrupt request signal, as
defined by the INT_POLARITY bit.
• An interrupt can be used to interrupt the host computer during the target mode (pass-through)
access or be used to service the FIFOs for programmed I/O accesses.
When bus mastering is invoked:
• An interrupt is not generated on the edge of an interrupt request signal.
• Only one PCI board can take control of the PCI bus at any given time during a bus-mastered
data transfer, and only one interrupt is permitted during this transfer. Therefore, an interrupt
cannot be generated at an arbitrary time. An interrupt is generated only after a predefined
number of data points have been transferred.
Bit combinations Data transfer mode Notes
Bit 7
ACCESSMODE1
Bit 6
ACCESSMODE0
0 0
Data is accessed via the target (pass-
through) mode of the AMCC S5933
bus controller. No bus mastering. Default upon
reset or
power-up
0 1
Data is accessed via the target (pass-
through) mode of the AMCC S5933
bus controller. No bus mastering
1 0
Data is accessed via the FIFO of the
AMCC S5933 bus controller. The
FIFO is accessible by the host as
programmed I/O or via
bus mastering. All ports, of
port group 0,
must be
configured as
inputs
1 1
Data is accessed via the FIFO of the
AMCC S5933 bus controller. The
FIFO is accessible by the host as
programmed I/O or via
bus mastering. All ports, of
port group 0,
must be
configured as
outputs