Keithley KPCI-3101 Series, User Manual

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i-4
E
edge gate type
high
2-21
low
2-21
encoding data
analog input
2-14
analog output
2-17
environmental specifications
A-7, A-8
error handling
6-2
errors, analog input
2-15
event counting
2-23, 3-21
event counting mode
A-11
event viewer
in DriverLINX
using for troubleshooting
6-2
expansion slot
requirement
1-5
expansion slot selection
3-5
external clock
A-11
A/D sample
2-7
C/T
2-20
external clock divider
maximum
A-11
minimum
A-11
external digital trigger
2-10, A-10
externally-retriggered scan mode
2-9
extra retrigger
A-9
F
falling-edge gate type
2-21
features
1-2
Flowchart
problem isolation Scheme A
C-3
problem isolation Scheme B
C-5
problem isolation Scheme C
C-10
problem isolation Scheme D
C-12
problem isolation Scheme E
C-13
problem isolation Scheme F
C-13
problem isolation Scheme G
C-13
formatting data
analog input
2-14
analog output
2-17
frequency
base clock
A-11
external A/D sample clock
2-7
external C/T clock
2-20
internal A/D sample clock
2-6, A-11
internal C/T clock
2-20, A-11
internal retrigger clock
2-8, A-9
frequency measurement
2-24
G
gain
analog input
2-4
analog inputs
calibrating
5-3
analog output
2-16
analog outputs
calibrating
5-3
number of
A-10
gain list, analog input
2-5
gap-free data
A-9
gate input signal
2-21
gate type
2-21
falling edge
2-21
high level
2-21
high-edge
A-11
high-level
A-11
internal
A-11
low-edge
A-11
low-level
A-11
none (software)
2-21
rising edge
2-21
GCL depth
A-10
generating continuous pulses
2-26
Grounding
KPCI-3101–4 Series I/O connector pin
assignments
3-7
H
hard disk, required free space
1-5
high-edge gate type
2-21, A-11
high-level gate type
2-21, A-11
high-to-low pulse output
2-22
I
inprocess buffers
A-9
input configuration
differential analog
3-15
single-ended analog
3-15
Input FIFO Overflow error
2-15
input ranges
2-4
inputs, analog
calibration
5-3
inserting the board
3-6
Installation
systematic problem isolation
C-5
Installation and Configuration
3-1
installing
DriverLINX
3-4