Keithley KPCI-3101 Series, User Manual

Page: 28 / 146

2-8 Principles of Operation KPCI-3101 — KPCI-3104 Series User’s Manual
Triggered scan mode
KPCI-3101–4 Series boards support two triggered scan modes: internally-retriggered and
externally-retriggered. These modes are described in the following subsections.
Internally-Retriggered Scan Mode
Use internally-retriggered scan mode if you want to accurately control both the period between
conversions of individual channels in a scan and the period between each scan. This mode is
useful when synchronizing or controlling external equipment, or when acquiring a buffer of data
on each trigger or retrigger. Using this mode, you can acquire up to 262,144 samples per trigger
(256 times per trigger x 1024-location channel-gain list).
When it detects an initial trigger, the KPCI-3101–4 Series board scans the channel-gain list a
specified number of times (up to 256), then waits for an internal retrigger to occur. When it
detects an internal retrigger, the board scans the channel-gain list the specified number of times,
then waits for another internal retrigger to occur. The process repeats continuously until either
the allocated buffers are filled or until you stop the operation; refer to
page 2-14 for more infor-
mation on buffers.
The sample rate is determined by the frequency of the A/D sample clock divided by the number
of entries in the channel-gain list; refer to
page 2-6 for more information on the A/D sample
clock. The conversion rate of each scan is determined by the frequency of the internal retrigger
clock. The internal retrigger clock is the Triggered Scan Counter on the board; the Triggered
Scan Counter is a 24-bit counter with a 20 MHz clock.
Using DriverLINX software, specify the frequency of the internal retrigger clock. The minimum
retrigger frequency is 1.2Hz (1.2 Samples/s).
Table 2-4 lists the maximum retrigger frequency
supported by the KPCI-3101–4 Series boards.
The appropriate retrigger frequency depends on a number of factors, determined by the follow-
ing equations:
For example, if you are using 16 channels in the channel-gain list (CGL), scanning the channel-
gain list 256 times every trigger or retrigger, and using an A/D sample clock with a frequency of
100kHz, set the maximum retrigger frequency to 24.41Hz, since
Table 2-4
Maximum retrigger frequency
Board
Maximum
Retrigger Frequency
KPCI-3101/3102 155kHz
KPCI-3103/3104 219kHz
Min. Retrigger Period
No. of CGL entries No. of CGLs per trigger
×
A/D sample clock frequency
---------------------------------------------------------------------------------------------------------------- 2
µ
s +
 
 
=
Max. Retrigger
1
Frequency Min. Retrigger Period
------------------------------------------------------------------------------- =
24.41Hz
1
16 256
× ( )
100kHz
-------------------------- 2
µ
s +
 
 
----------------------------------------------- =