JYTEK PXIe-69529 User Manual Download Page 4 | Manualshive

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Summary of Contents for PXIe-69529

Page 1: ...PXIe 69529 8 CH 24 Bit 204 8 kS s Dynamic Signal Acquisition Module User s Manual Manual Rev 1 00 Revision Date Jul 16 2016...

Page 2: ...03 China Tel 86 21 5047 5899 Fax 86 21 5047 5899 Email service jytek com Additional information aids and tips that help users perform tasks Information to prevent minor physical injury component damag...

Page 3: ...1 Functional Block Diagram 10 3 2 Analog Input Channel 10 3 2 1 Analog Input Front End Configuration 10 3 2 2 Input Range and Data Format 11 3 2 3 ADC and Analog Input Filter 12 3 2 4 DMA Data Transf...

Page 4: ...III...

Page 5: ...Input 4 Table 3 1 Input Range and Data Format 11 Table 3 2 Input Range Midscale Values 12 Table 3 3 ADC Sample Rates vs DDS Output Clock 12 Table 3 4 Preferred Characteristics for Analog Triggers 16...

Page 6: ...1 Analog Input Architecture 10 Figure 3 2 Linked List of PCI Address DMA Descriptors 13 Figure 3 3 Trigger Architecture 14 Figure 3 4 External Digital Trigger 14 Figure 3 5 Analog Trigger Conditions...

Page 7: ...EPE signal conditioning for accelerometers and microphones The PXIe 69529 is auto calibrated with an onboard reference circuit calibrating offset and acquiring analog input errors Following auto calib...

Page 8: ...fs 108 kS s Over voltage protection Differential 42 4V Pseudo differential positive terminal 42 4 V negative terminal unprotected rated at 2 5 V Input impedance 1M 50 between negative input and syste...

Page 9: ...agnitude Response Frequency Hz Magnitude dB Figure 1 1 Analog Input Channel Bandwidth 0 2 Vpp 0 1 2 3 4 5 6 7 8 9 10 12 10 8 6 4 2 0 Response when AC coupling enabled Frequency Hz Magnitude dB Figure...

Page 10: ...ctor Compatibility 3 3 V TTL 5 V tolerant Input high threshold 2 0 V Input low threshold VIL 0 8 V Maximum input overload 0 5 V to 5 5 V Trigger polarity Rising or falling edge Pulse width 20 ns minim...

Page 11: ...n programs JYTEK provides the following software development kits NET driver for Windows compatible with various application environments such as C VB NET VC NET VB VC BCB and Delphi 1 4 2 DSA DASK DS...

Page 12: ...6 1 5 Device Layout and I O Array All dimensions are in mm Figure 1 3 PXIe 69529 schematic...

Page 13: ...7 The PXIe 69529 I O array is labeled to indicate connectivity as shown Figure 1 4 PXIe 69529 I O Array...

Page 14: ...sily damaged by static electricity The module must be handled on a grounded anti static mat The operator must wear an anti static wristband grounded at the same point as the anti static mat Inspect th...

Page 15: ...he PXI chassis 3 Slide the module into the chassis until resistance is felt from the PXI connector 4 Push the ejector upwards and firmly seat the module into the chassis 5 Once the module is fully sea...

Page 16: ...DATA ADC Ctrl SCK Vref Vref 10k 10k 10k 10k Cal PGA Signal Switch X1 X10 Figure 3 1 Analog Input Architecture Differential and Pseudo Differential Input Configuration The PXIe 69529 provides both diff...

Page 17: ...h as accelerometers or microphones the PXIe 69529 provides an excitation current source The common excitation current is usually about 4mA for these IEPE sensors A DC voltage offset is generated due t...

Page 18: ...s as follows Sampling Rate DDS PLL CLK 8k to 54kS s 6 144 M 41 472 MHz 54K to 108kS s 13 824 M to 27 648 MHz 108K to 192kS s 20 736 M to 36 864 MHz Table 3 3 ADC Sample Rates vs DDS Output Clock Filte...

Page 19: ...mode there is no limitation on DMA data transfer size except the physical storage capacity of the system Users can also link descriptor nodes circularly to achieve a multibuffered DMA A linked list co...

Page 20: ...as analog trigger Software Trigger The software trigger generated by software command is asserted immediately following execution of specified function calls to begin the operation External Digital Tr...

Page 21: ...provided by PXI Trigger Bus multiple modules are easily synced When configured as input the PXIe 69529 serves as a slave module and can accept trigger signals from one of buses 0 through 7 When config...

Page 22: ...1 1 19 V 0 119 V 0 0V 0V FFFFFF 1 19 V 0 119 V 800001 9 99999881 V 0 999999881 V 800000 10 V 1 V Table 3 4 Preferred Characteristics for Analog Triggers Trigger Export The PXIe 69529 can export trigge...

Page 23: ...e PCIe clock Accordingly maximum delay time is the period of PCIe_CLK X 2 32 1 and minimum is the period of PCIe_CLK 8 ns Time Operation start Trigger Data Trigger Event Occurs Acquisition stop Begin...

Page 24: ...nboard timebase clock drives the sigma delta ADC with frequency exceeding the sample rate and produced by a PLL chip with output frequency programmable to superior resolution The PXIe 69529 accepts th...

Page 25: ...no requirement for additional cabling The eight interconnected lines on the PXI Express backplane labeled PXI Trigger Bus 0 7 provide a flexible interface for syncing multiple modules The PXIe 69529 u...

Page 26: ...smits the onboard ADC timebase through the PXI trigger bus As input the PXIe 69529 accepts the SSI_TIMEBASE signal as the source of the timebase 3 6 2 SSI_SYNC_START Before a SSI master issues SSI_TRI...

Page 27: ...et to hardware In the absence of user assignment the driver loads constants stored in bank 0 If constants from Bank 1 are to be loaded the preferred bank can be designated as boot bank by software Fol...

Page 28: ...power source settings Always install and operate equipment near an easily accessible electrical socket outlet Secure the power cord do not place any object on over the power cord Only install attach a...

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