19
3�5�3 Filter Delay in ADC
Filter delay indicates time required for data propagation through a converter. Both AI
channels experience filter delay due to filter circuitry and converter architecture, as
shown.
Update Rate (kS/s)
Filter Delay (samples)
8 K - 54 kS/s
13
54 K - 108 kS/s
13
108 K-192 kS/s
5
Table 3-6: ADC Filter Delay
3�6 Synchronizing Multiple Modules
The SSI (System Synchronization Interface) provides DAQ timing synchronization between
multiple cards, with a bidirectional SSI I/O providing flexible connection between cards
and allowing a single SSI master to output the signal to other slave modules. SSI signals
are designed for card synchronization only, not external devices. In the PXI Express form
factor, the PXI trigger bus built on the PXI Express backplane provides the necessary timing
signal connections. All SSI signals are routed to the XJ4 connector, with no requirement for
additional cabling. The eight interconnected lines on the PXI Express backplane, labeled PXI
Trigger Bus[0:7] provide a flexible interface for syncing multiple modules.
The PXIe-69529 utilizes the PXI Trigger Bus [0:7] as a System Synchronization Interface (SSI).
Flexible routing of timebase clock and trigger signals onto the PXI Trigger Bus enables the
PXIe-69529 to simplify synchronization between multiple modules.The bidirectional SSI I/O
provides flexible connection between modules, allowing the single SSI master PXIe-69529
to output the SSI signals to other slave modules. SSI timing signals and functions are as
shown, as is the SSI architecture.
SSI Timing Signal
Functionality
SSI_TIMEBASE
SSI master: issues TIMEBASE
SSI slave: accepts SSI_TIMEBASE to replace the
internal TIMEBASE signal.
SSI_SYNC_START
SSI master: issues internal SYNC_START
SSI slave: accepts SSI_SYNC_START as the digital
trigger signal.
SSI_AD_TRIG
SSI master: issues internal AD_TRIG
SSI slave: accepts SSI_AD_TRIG as the digital trigger
signal.
Table 3-7: SSI Timing Signal Definitions
