10
3 Operations
This chapter contains information regarding analog input, triggering and timing for the PXIe-
69529.
3.1 Functional Block Diagram
3�2 Analog Input Channel
3.2.1 Analog Input Front-End Configuration
24-bit ADC
JFET OPAMP
JFET OPAMP
330nF / 25V
CAL+
CAL-
IEPE-
1MR
1MR
330nF / 25V
SPST
SPST
IEPE+
49.9R
SPST
CARR
DATA
ADC Ctrl
SCK
Vref
Vref
10k
10k
10k
10k
Cal+
PGA
Signal Switch
X1
X10
Figure 3-1: Analog Input Architecture
Differential and Pseudo-Differential Input Configuration
The PXIe-69529 provides both differential and psuedo-differential input configurations,
with differential input mode providing voltage to the anode and cathode inputs of the
SMB connector according to signal voltage difference therebetween. If the signal source is
ground-referenced, differential input mode can be used for common-mode noise rejection.
