18
period of PCIe CLK. After the initial setup, no additional software intervention is required.
Time
Operation
start
Trigger
Data
1st Trigger Event Occurs
N samples
N samples
2nd Trigger Event Occurs
Figure 3-8: Re-Trigger Mode Acquisition
3�5 ADC Timing Control
3�5�1 Timebase
Figure 3-9: Timebase Architecture
An onboard timebase clock drives the sigma-delta ADC, with frequency exceeding the
sample rate and produced by a PLL chip, with output frequency programmable to superior
resolution. The PXIe- 69529 accepts the external 10MHz and 100MHz clocks from the PXI
Express backplane for improved synchronization between modules.
3�5�2 DDS Timing vs� ADC
Sampling Rate
8k – 54kS/s
54k - 108kS/s
108 k – 192kS/s
DDS(PLL) CLK
6.144 M-41.472 MHz 13.824 M-27.648 MHz 20.736 M-36.864 MHz
Table 3-5: Timing Relationship between ADC and PLL Clock
