M40e Packet Forwarding Engine Architecture
The Packet Forwarding Engine performs Layer 2 and Layer 3 packet switching.
•
Packet Forwarding Engine Components on page 60
•
Data Flow Through the Packet Forwarding Engine on page 60
Packet Forwarding Engine Components
The Packet Forwarding Engine is implemented in application-specific integrated circuits
(ASICs). It uses a centralized route lookup engine and shared memory.
The Packet Forwarding Engine architecture includes the components:
•
Midplane—Transports packets, notifications, and other signals between the FPCs and
the Packet Forwarding Engine (as well as other system components).
•
Physical Interface Card (PIC)—Physically connects the router to fiber-optic or digital
network media. A controller ASIC in each PIC performs control functions specific to
the PIC media type.
•
Flexible PIC Concentrators (FPCs)—House PICs and provide shared memory for
processing incoming and outgoing packets. Each FPC hosts two I/O Manager ASICs,
one active and one in standby mode. The active I/O Manager ASIC divides incoming
data packets into memory blocks (cells) before passing them to the active SFM, and
reassembles cells into data packets when the packets are ready for transmission. The
FPC also hosts two Packet Director ASICs—one concentrates incoming packets to the
active I/O Manager ASIC, and the other distributes outgoing packets to the appropriate
PICs on the FPC.
•
Switching and Forwarding Module (SFM)—Hosts an Internet Processor II ASIC, which
makes forwarding decisions, and two Distributed Buffer Manager ASICs: one distributes
data cells to the shared memory buffers on the FPCs and the other notifies the FPCs
of forwarding decisions for outgoing packets.
Data Flow Through the Packet Forwarding Engine
Use of ASICs promotes efficient movement of data packets through the system. Packets
flow through the Packet Forwarding Engine in the sequence (see Figure 35 on page 61):
1.
Packets arrive at an incoming PIC interface.
2.
The PIC passes the packets to the FPC, where the Packet Director ASIC directs them
to the active I/O Manager ASIC.
3.
The I/O Manager ASIC processes the packet headers, divides the packets into 64-byte
data cells, and passes the cells through the midplane to the SFM.
4.
A Distributed Buffer Manager ASIC on the SFM distributes the data cells throughout
the memory buffers located on and shared by all the FPCs.
5.
The Internet Processor II ASIC on the SFM performs a route lookup for each packet
and decides how to forward it.
Copyright © 2010, Juniper Networks, Inc.
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M40e Multiservice Edge Router Hardware Guide
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