JUMPtec superMOPSpro, Technical Manual, Page: 89 / 93

Signal Description
super MOPS pro
Copyright JUMP tec
 
Industrielle Computertechnik AG
Page: 89 of 93
DMA Timing Specification
This section specifies the timing for Direct Memory Access cycles (all time in ns):
No. Description MIN. TYP. MAX. Note
1 Clock period (Tclk ) 125
2 IOCHRDY setup to CLK 35
3 IOCHRDY hold from CLK 20
4 DRQ inactive delay from command 55
5 AEN setup to command 80
6 AEN hold from command 10
7 SA<23..0> setup to command 50
8 SA<23..0> hold from command 50
9 DACK setup to command 0
10 DACK hold from command 0
11 Extended Write delay 122 128
12 Write command width 80 1)
(Extended Write , 0 Waitstates)
13 Read inactive delay from Write 20
14 T/C delay from command 165
15 T/C hold from command 0
16 Read data setup 110
17 Read data hold 0
18 Write data delay after command 80 2)
19 Write data hold 15
Notes:
1) with programmable wait states from 1 to 4 CLK cycles
2) Note that this time cannot be extended by insertion of wait states