JUMPtec superMOPSpro, Technical Manual, Page: 78 / 93

Specifications
super MOPS pro
Copyright JUMP tec
 
Industrielle Computertechnik AG
Page: 78 of 93
PC/104-Bus Specification of super MOPS
Specification XT Bus X1, A1 - A32
Pin Signal Name Function CPU Module I/O Modules
Type Pullu
p Iol Ioh C Type Pullu
p Iol Ioh C
A1 /IOCHCK I/O Channel Check I 1K OC 12mA 120pF
A2 SD7 Data Bit 7 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
A3 SD6 Data Bit 6 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
A4 SD5 Data Bit 5 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
A5 SD4 Data Bit 4 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
A6 SD3 Data Bit 3 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
A7 SD2 Data Bit 2 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
A8 SD1 Data Bit 4 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
A9 SD0 Data Bit 3 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
A10 IOCHRDY I/O Channel Ready I 1K OC 12mA 120pF
A11 AEN Address Enable O 12mA 6mA 120pF I
A12 SA19 Address Bit 19 O 12mA 6mA 120pF I
A13 SA18 Address Bit 18 O 12mA 6mA 120pF I
A14 SA17 Address Bit 17 O 12mA 6mA 120pF I
A15 SA16 Address Bit 16 O 12mA 6mA 120pF I
A16 SA15 Address Bit 15 O 12mA 6mA 120pF I
A17 SA14 Address Bit 14 O 12mA 6mA 120pF I
A18 SA13 Address Bit 13 O 12mA 6mA 120pF I
A19 SA12 Address Bit 12 O 12mA 6mA 120pF I
A20 SA11 Address Bit 11 O 12mA 6mA 120pF I
A21 SA10 Address Bit 10 O 12mA 6mA 120pF I
A22 SA9 Address Bit 9 O 12mA 6mA 120pF I
A23 SA8 Address Bit 8 O 12mA 6mA 120pF I
A24 SA7 Address Bit 7 O 12mA 6mA 120pF I
A25 SA6 Address Bit 6 O 12mA 6mA 120pF I
A26 SA5 Address Bit 5 O 12mA 6mA 120pF I
A27 SA4 Address Bit 4 O 12mA 6mA 120pF I
A28 SA3 Address Bit 3 O 12mA 6mA 120pF I
A29 SA2 Address Bit 2 O 12mA 6mA 120pF I
A30 SA1 Address Bit 1 O 12mA 6mA 120pF I
A31 SA0 Address Bit 0 O 12mA 6mA 120pF I
A32 GND (Added) Ground
I = input O = output I/O = bidirectional signal OC = open collector output
1)
= the pullups on these signal lines have lower values then specified by the PC/104-
consortium
the changes have been made to improve timing characteristics for certain bus
architectures