Signal Description
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LA<17..23> (Latchable Address Bus)
output on CPU modules
input on any other module
These signals (unlatched) are used to address memory up to 16 MB.
/SBHE
(System Bus High Enable)
output on CPU modules
input on all other module
Bus High Enable indicates a transfer of data on the upper byte of the data bus (SD<8..15>).
16 bit I/O devices use SBHE to condition data bus buffers tied to SD<8..15>.
BALE
(Bus Address Latch Enable)
output from CPU modules
input on any other module
Bale is an active high pulse which is generated at the beginning of any bus cycle initiated by a
CPU module. It indicates when the SA<0..19>, LA<17..23>, AEN, and /SBHE signals are
valid.
AEN
(Address Enable)
output from CPU modules
input on any other module
AEN is an active high output that indicates a DMA transfer cycle, only resources with a active
/DACK signal should respond to the command lines when AEN is high.
Control Signal Group
/MEMR
(Memory Read)
output from CPU modules
input on any other module
/MEMR instructs memory devices to drive data onto the data bus. /MEMR is
active on all
memory read cycles.
/SMEMR
(System Memory Read)
output from CPU modules
input on any other module
/SMEMR instructs memory devices to drive data onto the data bus. /SMEMR is active on
memory read cycles to addresses below 1MB.
/MEMW
(Memory Write)
output from CPU modules
input on any other module
/MEMW instructs memory devices to store the data present on the data bus. /MEMW is
active on all memory write cycles.
/SMEMW
(System Memory Write)
output from CPU modules
input on any other module
/SMEMW instructs memory devices to store the data present on the data bus. /SMEMW is
active on all memory write cycles to address below 1MB.