JUMPtec superMOPSpro, Technical Manual, Page: 80 / 93

Specifications
super MOPS pro
Copyright JUMP tec
 
Industrielle Computertechnik AG
Page: 80 of 93
Specification AT Bus X2, C0 - C19
Pin Signal Name Function CPU Module I/O Modules
Type Pullu
p Iol Ioh C Type Pullu
p Iol Ioh C
C0 GND (Added) Ground
C1 /SBHE Bus High Enable O 12mA 6mA 120pF I
C2 LA23 Latch Address 23 O 12mA 6mA 120pF I
C3 LA22 Latch Address 22 O 12mA 6mA 120pF I
C4 LA21 Latch Address 21 O 12mA 6mA 120pF I
C5 LA20 Latch Address 20 O 12mA 6mA 120pF I
C6 LA19 Latch Address 19 O 12mA 6mA 120pF I
C7 LA18 Latch Address 18 O 12mA 6mA 120pF I
C8 LA17 Latch Address 17 O 12mA 6mA 120pF I
C9 /MEMR Mem.Read High 1M O 1K
1)
12mA 6mA 120pF I
C10 /MEMW Mem.Write High 1M O 1K
1)
12mA 6mA 120pF I
C11 SD8 Data Bit 8 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
C12 SD9 Data Bit 9 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
C13 SD10 Data Bit 10 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
C14 SD11 Data Bit 11 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
C15 SD12 Data Bit 12 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
C16 SD13 Data Bit 13 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
C17 SD14 Data Bit 14 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
C18 SD15 Data Bit 15 I/O 4K7
1)
12mA 6mA 120pF I/O 12mA 6mA 120pF
C19 GND (Added) Ground
I = input O = output I/O = bidirectional signal OC = open collector output
1)
= the pullups on these signal lines have lower values then specified by the PC/104-
consortium
the changes have been made to improve timing characteristics for certain bus
architectures
Specification AT Bus X2, D0 - D19
Pin Signal Name Function CPU Module I/O Modules
Type Pullu
p Iol Ioh C Type Pullu
p Iol Ioh C
D0 GND (Added) Ground
D1 /MEMCS16 16 Bit Mem.access I 300
1)
OC 12mA 120pF
D2 /IOCS16 16 Bit I/O access I 300
1)
OC 12mA 120pF
D3 IRQ10 Interrupt Request 10 I 4K7
1)
O 4mA 1mA 50pF
D4 IRQ11 Interrupt Request 11 I 4K7
1)
O 4mA 1mA 50pF
D5 IRQ12 Interrupt Request 12 I 4K7
1)
O 4mA 1mA 50pF
D6 IRQ15 Interrupt Request 13 I 4K7
1)
O 4mA 1mA 50pF
D7 IRQ14 Interrupt Request 14 I 4K7
1)
O 4mA 1mA 50pF
D8 /DACK0 DMA Acknowledge 0 O 4mA 1mA 50pF I 10K
D9 DRQ0 DMA Request 0 I 10K O 12mA 6mA 120pF
D10 /DACK5 DMA Acknowledge 5 O 4mA 1mA 50pF I 10K
D11 DRQ5 DMA Request 5 I 10K O 12mA 6mA 120pF
D12 /DACK6 DMA Acknowledge 6 O 4mA 1mA 50pF I 10K
D13 DRQ6 DMA Request 6 I 10K O 12mA 6mA 120pF
D14 /DACK7 DMA Acknowledge 7 O 4mA 1mA 50pF I 10K
D15 DRQ7 DMA Request 6 I 10K O 12mA 6mA 120pF
D16 +5V +5V
D17 /MASTER Bus Master Assert I 300
1)
OC 12mA 120pF
D18 GND Ground
D19 GND (Added) Ground
I = input O = output I/O = bidirectional signal OC = open Collector output
1)
= the pullups on these signal lines have lower values then specified by the PC/104-
consortium
the changes have been made to improve timing characteristics for certain bus
architectures