Signal Description
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/REFRESH (Memory Refresh)
output to CPU modules
input on any other module
/REFRESH is pulled low whenever a refresh cycle is initiated. A refresh cycle is activated
every 15,6 us to prevent loss of DRAM data.
/OWS
(0 Wait States)
input to CPU modules
output on any other module
The Zero wait state signal tells the CPU to complete the current bus cycle without inserting
the default wait states. By default the CPU inserts 4 wait states for 8 bit transfers and 1 wait
state for 16 bit transfers.
Special Function Signal Group
/MASTER
(MASTER bus request)
input to CPU modules
open collector output on any other module
This signal is used with a DRQ line to gain control of the system bus. A processor or DMA
controller on the I/O channel may issue a DRQ to a DMA channel in cascade mode and
receive a /DACK. Upon receiving the /DACK, a bus master may pull /MASTER low, which will
allow it to control the system address, data and control lines. After /MASTER is low, the bus
master must wait one system clock period before driving the address and data lines, and two
clock periods before issuing a read or write command. If this signal is held low for more than
15 us, system memory may be lost because of lack of refresh.
SYSCLK
(SYStem CLocK)
output from a CPU module
input on any other module
SYSCLK is supplied by the CPU module and has a nominal frequency of about 8 MHz with
40-60 % duty cycle. Slower and higher frequencies may be supplied by different CPU
modules. This signal is supplied at all times, except when the CPU module is in sleep mode.
OSC
(Oscillator frequency)
output on CPU modules
input on any other module
OSC is supplied by CPU modules. It has a nominal frequency of 14,31818 MHz and a duty
cycle of 40-60 %. This signal is supplied at all times, except when the CPU module is in sleep
mode.
RESETDRV (Bus RESET)
output on CPU modules
input on any other module
This active high output is system reset generated from CPU modules to reset external
devices.
DRQ<0..3, 5..7>
(DMA Request)
input to CPU modules
output on any other module
The asynchronous DMA request inputs are used by external devices to indicate when they
need service from the CPU modules DAM controllers. DRQ<0..3> are used for transfers
between 8 bit I/O adapters and system memory. DRQ<5..7> are used for transfers between
16 bit I/O adapters and system memory. DRQ4 is not available externally. All DRQ pins have
pullups on CPU modules.