JUMPtec superMOPSpro, Technical Manual, Page: 86 / 93

Signal Description
super MOPS pro
Copyright JUMP tec
 
Industrielle Computertechnik AG
Page: 86 of 93
Data Conversion and Swapping
Data Conversion
16 - bit transfers by the main CPU via the PC/104 - bus are converted into two 8 - bit
transfers (low and high Byte ) if the control signals MEMCS16* or IOCS16* are not asserted.
The higher Byte - Data (SD<15..8> ) is directed to SD <7..0> with SA0 =H during write
cycles and from SD <7..0> to SD <15..0 > with SA0 =H during read cycles. This operation is
transparent to the software .
Data Swapping
Data are swapped between SD <15..8 > and SD <7..0 > on the main CPU for odd Byte
transfers (SA0 =H) with 8 - bit devices on the
PC/104 - bus. Swapping occurs also during
DMA cycles (SA0 =H) if the devices on the PC/104 - bus is a 16 - bit memory device and an
8 - bit DMA channel is used for the transfer.
No. Description Min Typ Max Note
1 Clock period (Tclk) 125
2 BALE high width 54
3 SA<1..0> setup to BALE low 8
4 SBHE* setup to BALE low 20
5 SA<23..2> setup to BALE low 130
6a Command width 16 bit cycles (zero wait states) 125 2)
6b Command with 8 bit cycles (with 2 wait states) 325 3)
7 SA<1..0> setup to command zero cmd delay 8 1)
8 SBHE* setup to command zero cmd delay 20 1)
9 SA<23..2> setup to command zero cmd delay 130 1)
10 MEMCS16* , IOCS16* delay from SA<23..2> 80
11 MEMCS16* , IOCS16* hold after SA<23..2 0
12a SA<1..0> hold after command 23
12b SA<1..0> hold after SMEMR* or SMEMW* 18
13a SBHE* hold after command 23
13b SBHE* hold after SMEMR* or SMEMW* 18
14a SA<23..2> hold after command 30
14b SA<23..2> hold after SMEMR* or SMEMW* 25
15 Write Data setup to command active 6
16 Read Data setup to command inactive 65 1)
17a Write Data hold after command 45
17b Read Data hold after command 0
18 IOCHRDY setup to CLK 34
19 IOCHRDY hold after CLK 2
20 0WS* setup to CLK 20
21 0WS* hold after CLK 0
Notes:
1) Command delay programmable between 0 and 3 CLK/2 cycles seperately for 16
bit memory , 8 - bit memory and I/O cycles
2) Command width depends on the number of wait states (programmable from 0 to 3 CLK
cycles) and command delay (note 1)
3) Command width depends on the number of wait states (programmable from 2 to 5 CLK
cycles) and command delay (note 1)