Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
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Reference Number: 327043-001
being sent from the HA to the iMC. They deallocate after the CAS command has been issued to
memory. This includes both ISOCH and non-ISOCH requests.
RPQ_OCCUPANCY
• Title:
Read Pending Queue Occupancy
• Category:
RPQ Events
• Event Code:
0x80
• Max. Inc/Cyc:
22,
Register Restrictions:
0-3
• Definition:
Accumulates the occupancies of the Read Pending Queue each cycle. This can then be
used to calculate both the average occupancy (in conjunction with the number of cycles not empty)
and the average latency (in conjunction with the number of allocations). The RPQ is used to sched-
ule reads out to the memory controller and to track the requests. Requests allocate into the RPQ
soon after they enter the memory controller, and need credits for an entry in this buffer before
being sent from the HA to the iMC. They deallocate after the CAS command has been issued to
memory.
WPQ_CYCLES_FULL
• Title:
Write Pending Queue Full Cycles
• Category:
WPQ Events
• Event Code:
0x22
• Max. Inc/Cyc:
1,
Register Restrictions:
0-3
• Definition:
Counts the number of cycles when the Write Pending Queue is full. When the WPQ is
full, the HA will not be able to issue any additional read requests into the iMC. This count should be
similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just
somewhat smaller to account for the credit return overhead.
WPQ_CYCLES_NE
• Title:
Write Pending Queue Not Empty
• Category:
WPQ Events
• Event Code:
0x21
• Max. Inc/Cyc:
1,
Register Restrictions:
0-3
• Definition:
Counts the number of cycles that the Write Pending Queue is not empty. This can then
be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accu-
mulation count). The WPQ is used to schedule write out to the memory controller and to track the
writes. Requests allocate into the WPQ soon after they enter the memory controller, and need cred-
its for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being
issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest
of the system) as soon they have "posted" to the iMC. This is not to be confused with actually per-
forming the write to DRAM. Therefore, the average latency for this queue is actually not useful for
deconstruction intermediate write latencies.
WPQ_INSERTS
• Title:
Write Pending Queue Allocations
• Category:
WPQ Events
• Event Code:
0x20
• Max. Inc/Cyc:
1,
Register Restrictions:
0-3
• Definition:
Counts the number of allocations into the Write Pending Queue. This can then be used
to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ
is used to schedule write out to the memory controller and to track the writes. Requests allocate
into the WPQ soon after they enter the memory controller, and need credits for an entry in this buf-
fer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write
requests themselves are able to complete (from the perspective of the rest of the system) as soon
they have "posted" to the iMC.
