Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
90
Reference Number: 327043-001
The Intel® QPI performance monitor data registers are 48b wide.Should a counter overflow (a carry
out from bit 47), the counter will wrap and continue to collect events.
If accessible, software can continuously read the data registers without disabling event collection.
2.7.3.3
Intel® QPI Registers for Packet Mask/Match Facility
In addition to generic event counting, each port of the Intel® QPI Link Layer provides two pairs of
MATCH/MASK registers that allow a user to filter packet traffic serviced (crossing from an input port to
an output port) by the Intel® QPI Link Layer. Filtering can be performed according to the packet
Opcode, Message Class, Response, HNID and Physical Address. Program the selected Intel® QPI LL
counter to capture CTO_COUNT in order to capture the filter match as an event.
To use the match/mask facility :
a) Program the match/mask regs (see
Table 2-88, “Q_Py_PCI_PMON_PKT_MATCH1 Registers”
through
Table 2-91, “Q_Py_PCI_PMON_PKT_MASK0 Registers”
).
b) Set the counter’s control register event select to 0x38 (CTO_COUNT) to capture the mask/match
as a performance event.
The following table contains the packet traffic that can be monitored if one of the mask/match
registers was chosen to select the event.
edge_det
18
RW-V
0 When set to 1, rather than measuring the event in each cycle it
is active, the corresponding counter will increment when a 0 to 1
transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the event
is asserted.
NOTE: .edge_det is in series following .thresh, Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.
rst
17
WO
0 When set to 1, the corresponding counter will be cleared to 0.
rsv
16
RV
0 Reserved. SW must write to 0 else behavior is undefined.
umask
15:8
RW-V
0 Select subevents to be counted within the selected event.
ev_sel
7:0
RW-V
0 Select event to be counted.
Table 2-87. Q_Py_PCI_PMON_CTR{3-0} Register – Field Definitions
Field
Bits
Attr
HW
Reset
Val
Description
rsv
63:48
RV
0 Reserved (?)
event_count
47:0
RW-V
0 48-bit performance event counter
Table 2-86. Q_Py_PCI_PMON_CTL{3-0} Register – Field Definitions (Sheet 2 of 2)
Field
Bits
Attr
HW
Reset
Val
Description
