Reference Number: 327043-001
71
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
WPQ_OCCUPANCY
• Title:
Write Pending Queue Occupancy
• Category:
WPQ Events
• Event Code:
0x81
• Max. Inc/Cyc:
32,
Register Restrictions:
0-3
• Definition:
Accumulates the occupancies of the Write Pending Queue each cycle. This can then be
used to calculate both the average queue occupancy (in conjunction with the number of cycles not
empty) and the average latency (in conjunction with the number of allocations). The WPQ is used
to schedule write out to the memory controller and to track the writes. Requests allocate into the
WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before
being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests
themselves are able to complete (from the perspective of the rest of the system) as soon they have
"posted" to the iMC. This is not to be confused with actually performing the write to DRAM. There-
fore, the average latency for this queue is actually not useful for deconstruction intermediate write
latencies. So, we provide filtering based on if the request has posted or not. By using the "not
posted" filter, we can track how long writes spent in the iMC before completions were sent to the
HA. The "posted" filter, on the other hand, provides information about how much queueing is actu-
ally happenning in the iMC for writes before they are actually issued to memory. High average
occupancies will generally coincide with high write major mode counts.
WPQ_READ_HIT
• Title:
Write Pending Queue CAM Match
• Category:
WPQ Events
• Event Code:
0x23
• Max. Inc/Cyc:
1,
Register Restrictions:
0-3
• Definition:
Counts the number of times a request hits in the WPQ (write-pending queue). The iMC
allows writes and reads to pass up other writes to different addresses. Before a read or a write is
issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit,
they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit
will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will
simply update their relevant sections.
WPQ_WRITE_HIT
• Title:
Write Pending Queue CAM Match
• Category:
WPQ Events
• Event Code:
0x24
• Max. Inc/Cyc:
1,
Register Restrictions:
0-3
• Definition:
Counts the number of times a request hits in the WPQ (write-pending queue). The iMC
allows writes and reads to pass up other writes to different addresses. Before a read or a write is
issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit,
they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit
will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will
simply update their relevant sections.
