Reference Number: 327043-001
99
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
L1_POWER_CYCLES
• Title:
Cycles in L1
• Category:
POWER Events
• Event Code:
0x12
• Max. Inc/Cyc:
1,
Register Restrictions:
0-3
• Definition:
Number of Intel® QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally
shuts down a Intel® QPI link. Use edge detect to count the number of instances when the Intel®
QPI link entered L1. Link power states are per link and per direction, so for example the Tx direc-
tion could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a
good amount of time to exit this mode.
RxL0P_POWER_CYCLES
• Title:
Cycles in L0p
• Category:
POWER_RX Events
• Event Code:
0x10
• Max. Inc/Cyc:
1,
Register Restrictions:
0-3
• Definition:
Number of Intel® QPI qfclk cycles spent in L0p power mode. L0p is a mode where we
disable 1/2 of the Intel® QPI lanes, decreasing our bandwidth in order to save power. It increases
snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful
in NUMA optimized workloads that largely only utilize Intel® QPI for snoops and their responses.
Use edge detect to count the number of instances when the Intel® QPI link entered L0p. Link
power states are per link and per direction, so for example the Tx direction could be in one state
while Rx was in another.
• NOTE:
Using .edge_det to count transitions does not function if L1_POWER_CYCLES
RxL0_POWER_CYCLES
• Title:
Cycles in L0
• Category:
POWER_RX Events
• Event Code:
0x0F
• Max. Inc/Cyc:
1,
Register Restrictions:
0-3
• Definition:
Number of Intel® QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the
default mode which provides the highest performance with the most power. Use edge detect to
count the number of instances that the link entered L0. Link power states are per link and per
direction, so for example the Tx direction could be in one state while Rx was in another. The phy
layer sometimes leaves L0 for training, which will not be captured by this event.
Table 2-96. Unit Masks for DIRECT2CORE
Extension
umask
[15:8]
Description
SUCCESS
bxxxxxxx1
Spawn Success:
The spawn was successful. There were sufficient credits, and the
message was marked to spawn direct2core.
FAILURE_CREDITS
bxxxxxx1x
Spawn Failure - Egress Credits:
The spawn failed because there were not enough Egress credits. Had
there been enough credits, the spawn would have worked as the RBT
bit was set.
FAILURE_RBT
bxxxxx1xx
Spawn Failure - RBT Not Set:
The spawn failed because the route-back table (RBT) specified that
the transaction should not trigger a direct2core tranaction. This is
common for IO transactions. There were enough Egress credits.
FAILURE_CREDITS_RBT
bxxxx1xxx
Spawn Failure - Egress and RBT:
The spawn failed because there were not enough Egress credits AND
the RBT bit was not set.
