Intel Xeon Processor E5-2600, Monitoring Manual

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Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
48 Reference Number: 327043-001
The HA performance monitor data registers are 48-bit wide. Should a counter overflow (a carry out
from bit 47), the counter will wrap and continue to collect events.If accessible, software can
continuously read the data registers without disabling event collection.
In addition to generic event counting, each HA provides a pair of Address Match registers and an
Opcode Match register that allow a user to filter incoming packet traffic according to the packet
Opcode, Message Class and Physical Address. The ADDR_OPC_MATCH.FILT event is provided to
capture the filter match as an event. The fields are laid out as follows:
Note: Refer to Table 2-142, “Intel® QuickPath Interconnect Packet Message Classes” and
Table 2-143, “Opcode Match by Message Class” to determine the encodings of the B-
Box Match Register fields.
rsv 17:16 RV 0 Reserved. SW must write to 0 else behavior is undefined.
umask 15:8 RW-V 0 Select subevents to be counted within the selected event.
ev_sel 7:0 RW-V 0 Select event to be counted.
Table 2-36. HA_PCI_PMON_CTR{3-0} Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 63:48 RV 0 Reserved (?)
event_count 47:0 RW-V 0 48-bit performance event counter
Table 2-37. HA_PCI_PMON_BOX_OPCODEMATCH Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 31:6 RV 0 Reserved (?)
opc 5:0 RWS 0 Match to this incoming (? which polarity?) opcode
Table 2-38. HA_PCI_PMON_BOX_ADDRMATCH1 Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
rsv 31:14 RV 0 Reserved (?)
hi_addr 13:0 RWS 0 Match to this System Address - Most Significant 14b of cache
aligned address [45:32]
Table 2-35. HA_PCI_PMON_CTL{3-0} Register – Field Definitions (Sheet 2 of 2)
Field Bits Attr
HW
Reset
Val
Description