Reference Number: 327043-001
73
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
2.6.3.1
PCU Box Level PMON State
The following registers represent the state governing all box-level PMUs in the PCU.
In the case of the PCU, the PCU_MSR_PMON_BOX_CTL register governs what happens when a freeze
signal is received (.
frz_en
). It also provides the ability to manually freeze the counters in the box
(.
frz
) and reset the generic state (.
rst_ctrs
and .
rst_ctrl
).
The PCU provides two extra MSRs that provide additional static performance information to software
but exist outside of the PMON infrastructure (e.g. they can’t be frozen or reset). They are included for
the convenience of software developers need to efficiently access this data.
PCU_MSR_PMON_CTR0
0x0C36
64
PCU PMON Counter 0
Box-Level Filter
PCU_MSR_PMON_BOX_FILTER
0x0C34
32 PCU PMON Filter
Generic Counter Control
PCU_MSR_PMON_CTL3
0x0C33
32
PCU PMON Control for Counter 3
PCU_MSR_PMON_CTL2
0x0C32
32
PCU PMON Control for Counter 2
PCU_MSR_PMON_CTL1
0x0C31
32
PCU PMON Control for Counter 1
PCU_MSR_PMON_CTL0
0x0C30
32
PCU PMON Control for Counter 0
Box-Level Control/Status
PCU_MSR_PMON_BOX_CTL
0x0C24
32 PCU PMON Box-Wide Control
Fixed (Non-PMON) Counters
PCU_MSR_CORE_C6_CTR
0x03FD
64 Fixed C-State Residency Counter
PCU_MSR_CORE_C3_CTR
0x03FC
64 Fixed C-State Residency Counter
Table 2-74. PCU_MSR_PMON_BOX_CTL Register – Field Definitions
Field
Bits
Attr
HW
Reset
Val
Description
rsv
31:18
RV
0 Reserved (?)
rsv
17
RV
0 Reserved; SW must write to 0 else behavior is undefined.
frz_en
16
WO
0 Freeze Enable.
If set to 1 and a freeze signal is received, the counters will be
stopped or ‘frozen’, else the freeze signal will be ignored.
rsv
15:9
RV
0 Reserved (?)
frz
8
WO
0 Freeze.
If set to 1 and the .frz_en is 1, the counters in this box will be
frozen.
rsv
7:2
RV
0 Reserved (?)
rst_ctrs
1
WO
0 Reset Counters.
When set to 1, the Counter Registers will be reset to 0.
rst_ctrl
0
WO
0 Reset Control.
When set to 1, the Counter Control Registers will be reset to 0.
Table 2-73. PCU Performance Monitoring MSRs (Sheet 2 of 2)
MSR Name
MSR
Address
Size
(bits)
Description
