Intel® Server Board SE7520AF2 TPS
Functional Architecture
Revision 1.2
37
Intel order number C77866-003
3.1.4.4
Low Pin Count (LPC) Interface
The ICH5-R implements an LPC Interface as described in the Low Pin Count Interface
Specification, Revision 1.1. The Low Pin Count (LPC) Bridge function of the ICH5-R resides in
PCI Device 31: Function 0. In addition to the LPC bridge interface function, D31:F0 contains
other functional units including DMA, interrupt controllers, timers, power management, system
management, GPIO, and RTC.
On the Intel® Server Board SE7520AF2, the LPC bus is shared between the Super I/O SIO3
(National Semiconductor* PC87427), the mBMC and the IMM connector.
3.1.4.5
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the
seven DMA channels can be programmed to support fast Type-F transfers.
The ICH5-R supports two types of DMA: LPC and PC/PCI. LPC DMA and PC/PCI DMA use the
ICH5-R’s DMA controller. The PC/PCI protocol allows PCI-based peripherals to initiate DMA
cycles by encoding requests and grants via two PC/PC REQ#/GNT# pairs. LPC DMA is handled
through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] from the
host. Single, Demand, Verify, and Increment modes are supported on the LPC interface.
Channels 0–3 are 8 bit channels. Channels 5–7 are 16-bit channels. Channel 4 is reserved as a
generic bus master request.
The timer/counter block contains three counters that are equivalent in function to those found in
one 82C54 programmable interval timer. These three counters are combined to provide the
system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock
source for these three counters.
The ICH5-R provides an ISA-compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two 82C59 interrupt controllers. The two interrupt controllers are
cascaded so that 14 external and two internal interrupts are possible. In addition, the ICH5-R
supports a serial interrupt scheme. All of the registers in these modules can be read and
restored. This is required to save and restore system state after power has been removed and
restored to the platform.
3.1.4.6
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA-compatible PIC described in the previous section, the ICH5-R
incorporates the Advanced Programmable Interrupt Controller (APIC).
3.1.4.7
Universal Serial Bus (USB) Controller
The ICH5-R contains an Enhanced Host Controller Interface that supports USB high-speed
signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s which is 40 times faster
than full-speed USB. The ICH5-R also contains four Universal Host Controller Interface (UHCI)
controllers that support USB full-speed and low-speed signaling.
The Intel® Server Board SE7520AF2 makes use of five of the six USB 2.0 ports from the ICH5-
R: three available in the rear I/O area and two available via a DH10 header on the board that
