Intel® Server Board SE7520AF2 TPS
Table of Contents
Revision 1.2
Intel order number C77866-003
v
Table of Contents
1.
Introduction ........................................................................................................................ 21
1.1
Chapter Outline...................................................................................................... 21
1.2
Server Board Use Disclaimer ................................................................................ 22
2.
Server Board Overview...................................................................................................... 23
2.1
Intel® Server Board SE7520AF2 SKU Options ..................................................... 23
2.2
Intel® Server Board SE7520AF2 Feature Set ....................................................... 23
2.3
Server Board Layout.............................................................................................. 25
2.3.1
Component Placement .......................................................................................... 25
2.3.2
Mechanical Drawing .............................................................................................. 26
2.3.3
ATX I/O Layout ...................................................................................................... 27
3.
Functional Architecture ..................................................................................................... 29
3.1
Intel® E7520 Chipset............................................................................................. 30
3.1.1
Memory Controller Hub (MCH) .............................................................................. 30
3.1.2
PCI-X Hub (PXH) ................................................................................................... 34
3.1.3
IOP332 I/O Processor............................................................................................ 35
3.1.4
I/O Controller Hub (ICH5-R) .................................................................................. 35
3.2
Processor Sub-system........................................................................................... 39
3.2.1
Processor VRD ...................................................................................................... 40
3.2.2
Reset Configuration Logic ..................................................................................... 40
3.2.3
Processor Module Presence Detection ................................................................. 40
3.2.4
GTL2006................................................................................................................ 41
3.2.5
Common Enabling Kit (CEK) Design Support........................................................ 41
3.3
Memory Sub-System ............................................................................................. 41
3.3.1
Supported Memory ................................................................................................ 42
3.3.2
DIMM Population Rules and Supported Configurations ........................................ 42
3.3.3
Single Channel Operation...................................................................................... 44
3.3.4
I
2
C Bus................................................................................................................... 44
3.3.5
Memory Voltage Margining.................................................................................... 44
3.3.6
Memory RASUM Features..................................................................................... 44
3.4
I/O Sub-System ..................................................................................................... 51
3.4.1
PCI Subsystem ...................................................................................................... 51
3.4.2
Interrupt Routing .................................................................................................... 55