Intel Pentium II, Developer'S Manual

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INTEL CONFIDENTIAL
(until publication date)
CHAPTER 6
TEST ACCESS PORT (TAP)
This chapter describes the implementation of the P6 family test access port (TAP) logic. The
TAP complies with the IEEE 1149.1 (“JTAG”) test architecture standard. Basic functionality
of the 1149.1-compatible test logic is described here, but this chapter does not describe the
IEEE 1149.1 standard in detail. For this information, the reader is referred to the published
standard
1
, and to the many books currently available on the subject.
A simplified block diagram of the TAP is shown in Figure 6-1. The TAP logic consists of a
finite state machine controller, a serially-accessible instruction register, instruction decode
logic and data registers. The set of data registers includes those described in the 1149.1
standard (the bypass register, device ID register, BIST result register, and boundary scan
register).
6.1. INTERFACE
The TAP logic is accessed serially through 5 dedicated pins on the processor package:
•
TCK: The TAP clock signal
•
TMS: “Test mode select,” which controls the TAP finite state machine
•
TDI: “Test data input,” which inputs test instructions and data serially
•
TRST#: “Test reset,” for TAP logic reset
•
TDO: “Test data output,” through which test output is read serially
TMS, TDI and TDO operate synchronously with TCK (which is independent of any other
processor clock). TRST# is an asynchronous input signal.
1 ANSI/IEEE Std. 1149.1-1990 (including IEEE Std. 1149.1a-1993), “IEEE Standard Test Access Port and Boundary
Scan Architecture,” IEEE Press, Piscataway NJ, 1993.