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CONFIGURATION

5-8

8/26/97 1:02 PM CH05.DOC

INTEL CONFIDENTIAL

(until publication date)

Table 5-4. Pentium

II Processor Family Power-On Configuration Register (Continued)

Feature

Processor

Active Signals

Processor

Register

Bits

Read/Write

Default

Clock frequency ratios

LINT0, A20M#,

IGNNE#

D25=0, D24,
D23, D22
see Table 5-7

Read

N/A

Low power standby enable

N/A

D26

Read/Write

Enabled

Table 5-5. Pentium

II Processor Family Power-On Configuration Register

APIC Cluster ID Bit Field

APIC ID

D[17:16]

Table 5-6. Pentium

II Processor Family Power-On Configuration Register

Arbitration ID Configuration

Arbitration ID

D[21:20]

Table 5-7. Pentium

II Processor Family Power-On Configuration Register

Bus Frequency to Core Frequency Ratio Bit Field

D[25:22]

Ratio of Core Frequency to Bus Frequency

0010

0011

0101

7/2

0110

9/2

0100

Summary of Contents for Pentium II

Page 1: ...D Pentium II Processor Developer s Manual 243502 001 October 1997 1997...

Page 2: ...rs must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever f...

Page 3: ...Pipeline 2 9 2 3 2 Caches 2 13 2 4 WRITE BUFFERS 2 14 2 5 ADDITIONAL INFORMATION 2 14 2 6 ARCHITECTURE SUMMARY 2 14 CHAPTER 3 SYSTEM BUS OVERVIEW 3 1 SIGNALING ON THE PENTIUM II PROCESSOR SYSTEM BUS...

Page 4: ...5 4 5 1 11 BINIT Observation Policy 5 4 5 1 12 In Order Queue Pipelining 5 4 5 1 13 Power On Reset Vector 5 4 5 1 14 FRC Mode Enable 5 4 5 1 15 APIC Mode 5 5 5 1 16 APIC Cluster ID 5 5 5 1 17 Symmetr...

Page 5: ...II PROCESSOR SYSTEM BUS AC SPECIFICATIONS 7 19 CHAPTER 8 GTL INTERFACE SPECIFICATIONS 8 1 SYSTEM SPECIFICATION 8 1 8 1 1 System Bus Specifications 8 2 8 1 2 System AC Parameters Signal Quality 8 3 8 1...

Page 6: ...2 Boxed Processor Fan Heatsink Weight 12 4 12 2 3 Boxed Processor Retention Mechanism and Fan Heatsink Support 12 4 12 3 BOXED PROCESSOR REQUIREMENTS 12 8 12 3 1 Fan Heatsink Power Supply 12 8 12 4 T...

Page 7: ...6 6 7 1 GTL Bus Topology 7 1 7 2 Stop Clock State Machine 7 2 7 3 Timing Diagram of Clock Ratio Signals 7 7 7 4 Example Schematic for Clock Ratio Pin Sharing 7 8 7 5 BCLK to Core Logic Offset 7 25 7...

Page 8: ...rmal Plate Detail Dimensions 11 9 11 9 S E C Cartridge Substrate Dimensions Skirt not shown for clarity 11 10 11 10 S E C Cartridge Substrate Dimensions Cover Side View 11 10 11 11 S E C Cartridge Sub...

Page 9: ...equency to Core Frequency Ratio Bit Field 5 8 6 1 1149 1 Instructions in the Processor TAP 6 7 6 2 TAP Data Registers 6 8 6 3 Device ID Register 6 9 6 4 TAP Reset Actions 6 9 7 1 Core Frequency to Sys...

Page 10: ...3 Signal Listing in Order by Pin Number 11 13 11 4 Signal Listing in Order by Signal Name 11 18 12 1 Boxed Processor Fan Heatsink Spatial Dimensions 12 4 12 2 Boxed Processor Fan Heatsink Support Dime...

Page 11: ...E 1 Component Introduction...

Page 12: ......

Page 13: ...significant headroom for business desktop systems The Pentium II processor system bus operates in the same manner as the Pentium Pro processor system bus The Pentium II processor system bus uses GTL s...

Page 14: ...level For example when FLUSH is low a flush has been requested When NMI is high a non maskable interrupt has occurred In the case of signals where the name does not imply an active state but describes...

Page 15: ...l terms referred to in this and other related documentation Slot 1 The connector that the S E C cartridge plugs into just as the Pentium Pro processor uses Socket 8 Retention Mechanism A mechanical pi...

Page 16: ...r 243337 Pentium II Processor I O Buffer Models IBIS Format Electronic Form Intel Architecture Software Developer s Manual Volume I Basic Architecture Order Number 243190 Volume II Instruction Set Ref...

Page 17: ...E 2 Micro Architecture Overview...

Page 18: ......

Page 19: ...ch and execute phases and opens up a wide instruction window using an instruction pool This approach allows the execute phase of the processor to have much more visibility into the program instruction...

Page 20: ...ead stored back in the instruction pool awaiting in order retirement The core executes instructions depending upon their readiness to execute and not on their original program order and is therefore a...

Page 21: ...ad Store Fetch Decode Unit Dispatch Execute Unit Retire Unit 000926 Figure 2 3 The Three Core Engines Interface with Memory via Unified Caches The FETCH DECODE unit An in order unit that takes as inpu...

Page 22: ...Branch Target Buffer Register Alias Table Allocate 000927 Figure 2 4 Inside the Fetch Decode Unit The L1 Instruction Cache is a local instruction cache The Next_IP unit provides the L1 Instruction Cac...

Page 23: ...n array of Content Addressable Memory called the ReOrder Buffer ROB 2 2 2 The Dispatch Execute Unit The Dispatch unit selects ops from the instruction pool depending upon their status If the status in...

Page 24: ...correctly predict most of these branches but it can t correctly predict them all Consider a BTB that is correctly predicting the backward branch at the bottom of a loop eventually that loop is going...

Page 25: ...instruction The Retire Unit must not only notice which ops are complete it must also re impose the original program order on them It must also do this in the face of interrupts traps faults breakpoint...

Page 26: ...plete Stores are never performed speculatively since there is no transparent way to undo them Stores are also never re ordered among themselves A store is dispatched only when both the address and the...

Page 27: ...line The data cache is pseudo dual ported via interleaving with one port dedicated to loads and the other to stores Most simple operations integer ALU floating point add even floating point multiply c...

Page 28: ...ID1 Decode 1 stage decoder limits at most 3 macro instructions per cycle at most 6 ops 411 per cycle at most 3 ops per cycle exit the queue instructions 7 bytes in length RAT Register Allocation Deco...

Page 29: ...ry form have two to three ops Simple read modify write instructions are four ops Complex instructions generally have more than four ops therefore they will take multiple cycles to decode For the purpo...

Page 30: ...multiple pipelines grouped into five clusters Re order Buffer Writeback ROB wb Retirement RRF At most three ops are retired per cycle Taken branches must retire in the first slot Reservation station...

Page 31: ...e 3 3 4 Store Data Unit Latency 1 N A Throughput 1 cycle NOTES 1 The FMUL unit cannot accept a second FMUL within the cycle after it has accepted the first This is NOT the same as only being able to d...

Page 32: ...to each pipe in Pentium processors without MMX technology Performance of critical loops can be improved by scheduling the writes to memory when you expect to see write misses you should schedule the...

Page 33: ...E 3 System Bus Overview...

Page 34: ......

Page 35: ...input paths between the buffer and the latch stage thus keeping setup and hold times constant for all bus signals following the latched protocol The System bus requires that every input be sampled du...

Page 36: ...s are grouped according to function 3 2 1 Execution Control Signals Table 3 1 lists the execution control signals which control the execution and initialization of the processor Table 3 1 Execution Co...

Page 37: ...cution The assertion of STPCLK has no effect on the bus clock The SLP signal is the Sleep signal When asserted in Stop Grant state the processor enters a new low power state the Sleep state During Sle...

Page 38: ...led active no symmetric agent issues another unlocked bus transaction until BPRI is sampled inactive The priority agent is always the next bus owner BNR can be asserted by any bus agent to block furth...

Page 39: ...4 gigabits 64 GByte Address bits 2 1 and 0 are mapped into byte enable signals for 1 to 8 byte transfers The address signals are protected by the AP 1 0 pins AP1 covers A 35 24 AP0 covers A 23 3 AP 1...

Page 40: ...e transaction from the In order Queue by generating the appropriate response 3 2 5 Response Signals The response signal group see Table 3 5 provides response information to the requesting agent Table...

Page 41: ...lock data transfer DBSY need not be asserted for single clock data transfers if no wait states are needed The D 63 0 signals provide a 64 bit data path between bus agents The DEP 7 0 signals provide o...

Page 42: ...the BINIT driver is disabled BINIT is never asserted and no action is taken on bus errors Regardless of whether the BINIT driver is enabled the Pentium II processor supports two modes of operation tha...

Page 43: ...3 8 contains signals defined for compatibility within the Intel Architecture processor family Table 3 8 PC Compatibility Signals Type Signal Names Floating Point Error FERR Ignore Numeric Error IGNNE...

Page 44: ...handler 3 2 9 Diagnostic Signals The BP 3 2 signals are the System Support group Breakpoint signals They are outputs from the processor that indicate the status of breakpoints The BPM 1 0 signals are...

Page 45: ...E 4 Data Integrity...

Page 46: ......

Page 47: ...hitecture Several model specific registers are defined for reporting error status Hardware corrected errors are reported to registers associated with the unit reporting the error Unrecoverable errors...

Page 48: ...g parity or ECC Eight ECC bits protect the data bus Single bit data ECC errors are automatically corrected A two bit parity code protects the address bus Any address parity error on the address bus wh...

Page 49: ...r checking or with ECC If ECC is selected single bit errors can be corrected and double bit errors can be detected Corrected single bit ECC errors are logged as recoverable errors All other errors are...

Page 50: ...e correct parity A correct parity signal is high if all covered signals are high or if an even number of covered signals are low A correct parity signal is low if an odd number of covered signals are...

Page 51: ...E 5 Configuration...

Page 52: ......

Page 53: ...ctive transition of RESET and be deasserted two clocks after the active to inactive transition of RESET see Figure 5 1 The IGNNE A20M and LINT 1 0 signals must meet a setup time of 1 ms to the active...

Page 54: ...rs enabled or disabled Software BINIT error driving policy enabled or disabled Software BINIT error observation policy enabled or disabled Hardware In order Queue depth 1 or 8 Hardware Power on reset...

Page 55: ...s optional After active RESET address bus parity error driving is always disabled It may be enabled under software control 5 1 6 AERR Observation Policy The AERR input receiver is enabled if A8 is obs...

Page 56: ...RESET The Pentium II processor requires BINIT observation to be enabled during normal operation 5 1 12 In Order Queue Pipelining Pentium II processor system bus agents are configured to an In order Qu...

Page 57: ...esignate electrical levels 5 1 17 Symmetric Agent Arbitration ID The Pentium II processor system bus supports symmetric distributed arbitration among one to two agents Each processor identifies its in...

Page 58: ...tration ID L H H 0 H H H 1 L H L 0 master H H L 0 checker NOTE 1 L and H designate electrical levels 5 1 18 Low Power Standby Enable A configuration register bit which enables distribution of the core...

Page 59: ...Processor Active Signals Processor Register Bits Read Write Default Output tristate enabled FLUSH D8 1 Read N A Execute BIST INIT D9 1 Read N A Data error checking enabled N A D1 1 Read Write Disabled...

Page 60: ...Write Enabled Table 5 5 Pentium II Processor Family Power On Configuration Register APIC Cluster ID Bit Field APIC ID D 17 16 0 00 1 01 2 10 3 11 Table 5 6 Pentium II Processor Family Power On Config...

Page 61: ...F0 During initialization each processor begins active BNR sequencing from the RESET signal s active to inactive transition until it is able to accept though not necessarily issue bus transactions Sign...

Page 62: ......

Page 63: ...E 6 Test Access Port TAP...

Page 64: ......

Page 65: ...n decode logic and data registers The set of data registers includes those described in the 1149 1 standard the bypass register device ID register BIST result register and boundary scan register 6 1 I...

Page 66: ...essed through a 1149 1 compliant TAP controller finite state machine This finite state machine shown in Figure 6 2 contains a reset state a run test idle state and two major branches These branches al...

Page 67: ...tely when TRST is pulled active and automatically upon power up of the processor The TAP controller cannot leave this state as long as TRST is held active Run Test Idle This is the idle state of the T...

Page 68: ...n the falling edge of TCK The parallel latched output of the selected Data Register does not change while new data is being shifted in Exit1 DR This is a temporary state All registers retain their pre...

Page 69: ...path between TDI and TDO In Update IR the shift register contents are latched in parallel into the actual instruction register Note that the only time the outputs of the actual instruction register c...

Page 70: ...ay as the instruction register with components i e either the capture or update functionality removed from the basic structure as needed Data registers are accessed just as the instruction register is...

Page 71: ...ter HIGHZ 001000 Floated Bypass Reset bypass reg Shift data register BYPASS 111111 Bypass Reset bypass reg Shift data register Reserved All other Reserved Reserved Reserved Reserved Reserved Reserved...

Page 72: ...a registers which can be accessed through the TAP The MSB of the register is connected to TDI for writing and the LSB of the register is connected to TDO for reading when that register is selected Tab...

Page 73: ...be driven low during TAP operation For more information on Boundary Scan refer to the Pentium II Processor Boundary Scan Description Language files at the Intel developer s website at developer intel...

Page 74: ...on the processor This automatically asynchronously resets the TAP controller Assert the TRST pin at any time This asynchronously resets the TAP controller Hold the TMS pin high for 5 consecutive cycl...

Page 75: ...E 7 Electrical Specifications...

Page 76: ......

Page 77: ...ace is used to pull the bus up to the high voltage level and to control reflections on the transmission line VREF is used by the receivers to determine if a signal is a logical 0 or a logical 1 and is...

Page 78: ...erted 3 Stop Grant State BCLK running Snoops and interrupts allowed SLP Asserted SLP De asserted 5 Sleep State BCLK running No snoops or interrupts allowed BCLK Input Stopped BCLK Input Restarted 6 De...

Page 79: ...ssor will return to the AutoHALT state The system can generate a STPCLK while the processor is in the AutoHALT Power Down state When the system deasserts the STPCLK interrupt the processor will return...

Page 80: ...essor to enter the Sleep state The SLP pin is not recognized in the Normal or AutoHALT states Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause...

Page 81: ...cache during AutoHALT Power Down or Stop Grant states Entrance into the HALT Grant Snoop state will allow the L2 cache to be snooped similar to Normal state When the processor is in Sleep and Deep Sle...

Page 82: ...a reduced lifetime of the component 7 4 1 Pentium II Processor VccCORE Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR This can be accomplis...

Page 83: ...uency LINT 1 LINT 0 A20M IGNNE 1 2 2 L L L L 1 4 L L H L 2 7 L H L H 2 9 L H H L 1 2 2 H H H H NOTES 1 L and H designate electrical levels 2 This combination exists for safe power on only The processo...

Page 84: ...V 000918 Figure 7 4 Example Schematic for Clock Ratio Pin Sharing If the multiplexer were powered by Vcc2 5 a pull down could be used on CRESET instead of the four pull up resistors between the multip...

Page 85: ...frequency multipliers to each processor the design shown in Figure 7 4 would require two multiplexers 7 6 VOLTAGE IDENTIFICATION There are five voltage identification pins on the Pentium II processor...

Page 86: ...05 4 1 1 1 1 1 No Core 1 1 1 1 0 2 1 4 1 1 1 0 1 2 2 4 1 1 1 0 0 2 3 4 1 1 0 1 1 2 4 4 1 1 0 1 0 2 5 4 1 1 0 0 1 2 6 4 1 1 0 0 0 2 7 4 1 0 1 1 1 2 8 4 1 0 1 1 0 2 9 1 0 1 0 1 3 0 1 0 1 0 0 3 1 1 0 0 1...

Page 87: ...o VccCORE VccL2 VSS or to any signal can result in component malfunction or incompatibility with future Slot 1 products See Section 5 2 for a pin listing of the processor and the location of each Rese...

Page 88: ...term GTL Input refers to the GTL input group as well as the GTL I O group when receiving Similarly GTL Output refers to the GTL output group as well as the GTL I O group when driving The CMOS Clock AP...

Page 89: ...er the agent ID is determined See Appendix A for more information 2 See Section A 1 35 for information on the PWRGOOD signal 3 See Section 7 2 5 and Section A 1 42 for information on the SLP signal 4...

Page 90: ...nctional operation at the absolute maximum and minimum is not implied nor guaranteed The processor should not receive a clock while subjected to these conditions Functional operating conditions are gi...

Page 91: ...e See Table 7 6 2 This rating applies to the VccCORE VccL2 Vcc5 and any input except as noted below to the processor 3 Parameter applies to CMOS APIC and TAP bus signal groups only 4 The mechanical in...

Page 92: ...level 0 185 0 185 V 6 IccCORE ICC for VccCORE 233 MHz 266 MHz 300 MHz 6 90 7 80 8 70 11 80 12 70 14 20 A A A 2 7 8 16 2 7 8 16 2 7 8 16 IccL2 ICC for L2 cache 0 50 1 40 A 3 8 Ivtt Termination voltage...

Page 93: ...erating system These numbers are meant as a guideline only not a guaranteed specification Actual measurements will vary based upon system environmental conditions and configuration 8 Max ICC measureme...

Page 94: ...t 15 A 3 NOTES 1 Parameter measured into a 50 resistor to 1 5V 2 0 VIN 2 5V 5 3 0 VOUT 2 5V 5 Table 7 8 Non GTL Signal Groups DC Specifications Symbol Parameter Min Max Unit Notes VIL Input Low Voltag...

Page 95: ...cache bus frequencies Table 7 11 contains the GTL specifications Table 7 12 contains the CMOS signal group specifications Table 7 13 contains timings for the reset conditions Table 7 14 covers APIC bu...

Page 96: ...during initialization as described in Section 7 5 Table 7 10 shows the supported ratios for each processor 4 The BCLK period allows a 0 5 ns tolerance for clock driver variation 5 The BCLK offset tim...

Page 97: ...Figure Notes T7 GTL Output Valid Delay 1 07 6 37 ns 7 7 3 T8 GTL Input Setup Time 2 53 ns 7 8 4 5 6 T9 GTL Input Hold Time 1 53 ns 7 8 7 T10 RESET Pulse Width 1 00 ms 7 11 8 NOTES 1 Not 100 tested Spe...

Page 98: ...ure recognition on a specific clock the setup and hold times with respect to BCLK must be met 6 INTR and NMI are only valid during APIC disable mode LINT 1 0 are only valid during APIC enabled mode 7...

Page 99: ...D 1 0 Valid Delay 3 0 12 0 ns 7 7 4 5 6 NOTES 1 Not 100 tested Specified by design characterization 2 All AC timings for the APIC clock and APIC I O signals are referenced to the PICCLK rising edge at...

Page 100: ...2 4 7 8 T44 Non Test Inputs Hold Time 14 5 ns 7 12 4 7 8 NOTES 1 All AC timings for the TAP signals are referenced to the TCK rising edge at 0 70V at the processor edge fingers All TAP signal timings...

Page 101: ...receive the signal with a reference at 1 25V Timings for other components on the baseboard should use a BCLK reference voltage of 1 25V All GTL signal timings are referenced at 1 00V at the Slot 1 con...

Page 102: ...0V for GTL signal group 1 25V for CMOS APIC and TAP signal groups Tpw 000762b Figure 7 7 System Bus Valid Delay Timings CLK Signal V Valid Ts T8 T12 T27 Setup Time Th T9 T13 T28 Hold Time V 1 0V for...

Page 103: ...Input Setup Time Tv T10 RESET Pulse Width Tw T16 Reset Configuration Signals A 14 5 BR0 FLUSH INIT Setup Time Tx T17 Reset Configuration Signals A 14 5 BR0 FLUSH INIT Hold Time T20 Reset Configuratio...

Page 104: ...uration A20M IGNNE LINT 1 0 000765b Ta Tb Tc Ta T15 PWRGOOD Inactive Pulse Width Tb T10 RESET Pulse Width Tc T20 Reset Configuration Signals A20M IGNNE LINT 1 0 Hold Time Valid Ratio V REF V CORE CC V...

Page 105: ...etup Time Ts T44 All Non Test Inputs Hold Time Tu T40 TDO Float Delay Tv T37 TDI TMS Setup Time Tw T38 TDI TMS Hold Time Tx T39 TDO Valid Delay Ty T41 All Non Test Outputs Valid Delay Tz T42 All Non T...

Page 106: ......

Page 107: ...E 8 GTL Interface Specifications...

Page 108: ......

Page 109: ...pacitance and package stub length and a receiver threshold VREF that is proportional to the termination voltage The specification is given in two parts The first is the system specification which desc...

Page 110: ...e placed electrically between the ends of the signal traces and the VTT voltage supply and generally are chosen to approximate the substrate impedance The valid high and low levels are determined by t...

Page 111: ...s specified in Table 7 6 This is measured at the processor edge fingers It is recommended that VTT be held to 1 5 3 during system bus idle 3 VREF is generated by the processor to be 2 3 VTT nominally...

Page 112: ...in 250mV of VREF at the processor edge fingers although specific devices may allow more ringing and loosen this specification See Section 8 1 2 1 for more details VREF 250 mV The overshoot undershoot...

Page 113: ...to well controlled ringing into the overdrive zone or even to brief re crossing of the switching threshold VREF Such ringback tolerant receivers give the system designer more design freedom and if no...

Page 114: ...given value of it is likely that will be the longest for the slowest input edge rate of 0 3V ns Furthermore there may be some dependence between and lower starting voltages than VREF 0 2V for Lo to Hi...

Page 115: ...erate any ringback would show the following values for the above parameters 0V TSU 200 mV undefined 200 mV A receiver which tolerates 50 mV of ringback would show the following values for the above pa...

Page 116: ...ent is similar for a simple Hi to Lo transition Notice that timing is measured at the driver and receiver pins while signal integrity is observed at the receiver chip pad When signal integrity at the...

Page 117: ...Such a requirement would always yield signals with an average edge rate 0 3V ns but which could have instantaneous slopes that are lower or higher than 0 3V ns as long as they do not cause a crossing...

Page 118: ...last crossing of VREF 200 mV using a line with a slope of 0 8V ns the maximum allowed rising edge rate This yields a new VREF crossing point to be used for the flight time calculation Figure 8 7 repr...

Page 119: ...taken when using the 0 8V ns extrapolation The extrapolation is invalid whenever it yields a VREF crossing that occurs earlier than when the signal s actual edge crosses VREF In that case flight time...

Page 120: ...adjustment factor that accounts for timing pushout seen when multiple bits change state at the same time The factors that contribute to the adjustment factor include crosstalk on the PCB substrate an...

Page 121: ...DC parameters Table 8 3 I O Buffer DC Parameters Symbol Parameter Min Max Units Notes VOL Driver Output Low Voltage 0 600 V 1 VIH Receiver Input High Voltage VREF 0 2 V 2 VIL Receiver Input Low Voltag...

Page 122: ...dge rate specifications 3 The minimum edge rate is a design target and slower edge rates can be acceptable although there is a timing impact associated with them in the form of an increase in flight t...

Page 123: ...terconnect Clock NOTE This is specific to the Pentium processor Other GTL components may be specified to a different test load 000955 Figure 8 9 Test Load for Measuring Output AC Timings Driver Pin in...

Page 124: ...IN_LOW_MAX VREF 200 mV and goes to VIN_HIGH_MIN VREF 200 mV at a slow edge rate of 0 3V ns with the process temperature voltage and VREF_INTERNAL of the receiver set to the worst longest TSU corner va...

Page 125: ...ed when the input barely meets minimum setup time see definition of setup time above However for current GTL systems setup time is expected to be met well beyond the minimum required in cases where ho...

Page 126: ...rate of 0 8V ns with the process temperature voltage and VREF_INTERNAL of the receiver set to the fastest or best corner values yielding the longest THOLD Here VREF is the external system reference v...

Page 127: ...he Setup Time equation given earlier in Section 8 1 3 TFLIGHT_MAX Clock Period TCO MAX TSU MIN TCLK_SKEW MAX TCLK_JITTER MAX CLKADJ TADJ As an example for two identical agents located on opposite ends...

Page 128: ...nd must be held at the receiver relative to the same clock edge THOLD TCO MIN TFLIGHT MIN TCLK SKEW MAX CLKADJ Assumptions TCO MIN 1 07 ns Assumed of max TCLK SKEW MAX 0 45 ns Driver to receiver skew...

Page 129: ...E 9 Signal Quality Specifications...

Page 130: ......

Page 131: ...ameter Min Nom Max Unit Figure Notes V1 BCLK VIL 0 7 V 9 1 V2 BCLK VIH 1 8 V 9 1 V3 VIN Absolute Voltage Range 0 5 3 3 V 9 1 Overshoot Undershoot V4 Rising Edge Ringback 2 0 V 9 1 Absolute Value 1 V5...

Page 132: ...SIGNAL QUALITY SPECIFICATIONS E 9 2 T3 V3 V5 V3 V2 V1 V7 V6 T6 T4 T5 V4 000808 Figure 9 1 BCLK TCK PICCLK Generic Clock Waveform at the Processor Edge Fingers...

Page 133: ...3 1 Overshoot Undershoot Guidelines Overshoot or undershoot is the absolute value of the maximum voltage above the nominal high voltage or below VSS The overshoot undershoot guideline limits transitio...

Page 134: ...eving its maximum absolute value See Figure 9 2 for an illustration of ringback Excessive ringback can cause false signal detection or extend the propagation delay The ringback specification applies t...

Page 135: ...otal signal swing VHI VLO above and below its final value A signal should be within the settling limits of its final value when either in its high state or low state before it transitions again Signal...

Page 136: ......

Page 137: ...E 10 Thermal Specifications and Design Considerations...

Page 138: ......

Page 139: ...ble 10 1 provides the thermal design power dissipation for the Pentium II processor While the processor core dissipates the majority of the thermal power the thermal power dissipated by the L2 cache a...

Page 140: ...The heatsink should be designed to dissipate the thermal plate power See Table 10 1 for Pentium II processor thermal design specifications 10 2 PENTIUM II PROCESSOR THERMAL ANALYSIS 10 2 1 Thermal Sol...

Page 141: ...e Pentium II processor operation the thermal plate temperature TPLATE must be maintained at or below the maximum TPLATE temperature and at or above the minimum TPLATE temperature specified in Table 10...

Page 142: ...089 Measure from edge of thermal plate Cover Measure T at this point PLATE Processor Core Substrate All dimensions in inches 0 35 R Recommended location of thermal grease application Approx location f...

Page 143: ...ut should be smaller than 0 150 in diameter Make sure there is no contact between the thermocouple cement and heatsink base This contact will affect the thermocouple reading 10 2 2 2 COVER TEMPERATURE...

Page 144: ...cement 10 3 THERMAL SOLUTION ATTACH METHODS The design of the thermal plate is intended to support two different attach methods heatsink clips and Rivscrews Figure 11 4 and Figure 11 6 show the therma...

Page 145: ...rmal plate The clearance of the thermal plate to the internal processor substrate is a minimum 0 125 illustrated in Figure 10 7 Figure 10 8 and Figure 10 6 The clips should be designed such that they...

Page 146: ...s Processor Core 0 089 Max Depth 000877a Figure 10 7 Processor with an Example Low Profile Heatsink Attached using Spring Clips 0 089 Max Depth Thermal Plate Spring Clip Cover Processor Substrate All...

Page 147: ...gure 10 11 for details of heatsink requirements for use with Rivscrews For other heatsink base thicknesses contact your vendor for other Rivscrew parts that would be required 3 0 Maximum Total Heatsin...

Page 148: ...THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS E 10 10 Y X H ole is 4 x 0 150 0 005 0 305 Heatsink A ll dimensions in inches 000903a Figure 10 11 General Rivscrew Heatsink Mechanical Recommendations...

Page 149: ...E 11 S E C Cartridge Mechanical Specifications...

Page 150: ......

Page 151: ...II processor s thermal plate and latch arms Figure 11 9 through Figure 11 12 provide details of the Pentium II processor s substrate and markings The processor edge connector defined in this document...

Page 152: ...UGH FIGURE 11 12 Unless otherwise specified the following drawings are dimensioned in inches All dimensions provided with tolerances are guaranteed to be met for all normal production product Figures...

Page 153: ...CARTRIDGE MECHANICAL SPECIFICATIONS 11 3 Skirt Left Latch Arm Right Latch Arm Cover Thermal Plate Right Latch Arm Left Latch Arm Cover 000893a Figure 11 1 S E C Cartridge Thermal Plate and Cover Side...

Page 154: ...S E C CARTRIDGE MECHANICAL SPECIFICATIONS E 11 4 001055a Figure 11 2 S E C Cartridge Top and Side Views...

Page 155: ...E S E C CARTRIDGE MECHANICAL SPECIFICATIONS 11 5 001054a Figure 11 3 S E C Cartridge Bottom Side View...

Page 156: ...2 473 0 016 2 070 0 020 These dimensions are from the bottom of the substrate edge fingers 001053a Figure 11 4 S E C Cartridge Thermal Plate Side Dimensions 2 50 1 25 0 001 1 000 x 1 000 001052a NOTE...

Page 157: ...E S E C CARTRIDGE MECHANICAL SPECIFICATIONS 11 7 000312JBM Figure 11 6 S E C Cartridge Thermal Plate Attachment Detail Dimensions...

Page 158: ...IFICATIONS E 11 8 2X 0 174 0 005 2X 0 488 0 010 2X 0 238 0 010 2X 0 103 0 005 2X 0 647 0 015 2X 0 253 0 010 2X 0 058 0 005 2X 0 136 0 005 Left 001056a Figure 11 7 S E C Cartridge Latch Arm Thermal Pla...

Page 159: ...084 0 060 0 122 0 075 R 0 015 0 060 0 055 0 316 0 058 0 277 0 116 0 291 Detail C Detail D Detail E 45 0 120 Min 0 082 0 276 0 216 001057a NOTE All dimensions without tolerance information are conside...

Page 160: ...imensions without tolerance information are considered reference dimensions only Figure 11 9 S E C Cartridge Substrate Dimensions Skirt not shown for clarity Pin B121 Pin B1 Substrate Cover NOTE Cover...

Page 161: ...1 X 0 016 0 002 0 045 0 236 0 074 0 002 20 008 L Z W M 05 002 Pad to Pad 121 X 0 043 0 002 20 008 L Z W M 05 002 Pad to Pad L L 0 356 Min 0 138 Min 0 008 0 010 001060b NOTE All dimensions without tole...

Page 162: ...R O C E S S O R Dynamic Mark Area pentium II P R O C E S S O R with MMX technology pentium II P R O C E S S O R with MMX technology 000978a Figure 11 12 S E C Cartridge Mark Locations Processor Markin...

Page 163: ...MOS Input A9 TDI JTAG Input B9 VCC_VTT GTL VTT Supply A10 GND VSS B10 TMS JTAG Input A11 TDO JTAG Output B11 TRST JTAG Input A12 PWRGOOD CMOS Input B12 Reserved Reserved for Future Use A13 TESTHI CMOS...

Page 164: ...VSS B34 D 56 GTL I O A35 D 60 GTL I O B35 D 50 GTL I O A36 D 53 GTL I O B36 D 54 GTL I O A37 D 57 GTL I O B37 VCC_CORE Processor Core VCC A38 GND VSS B38 D 59 GTL I O A39 D 46 GTL I O B39 D 48 GTL I O...

Page 165: ...O B61 EMI EMI Management A62 GND VSS B62 D 20 GTL I O A63 D 13 GTL I O B63 D 17 GTL I O A64 D 11 GTL I O B64 D 15 GTL I O A65 D 10 GTL I O B65 VCC_CORE Processor Core VCC A66 GND VSS B66 D 12 GTL I O...

Page 166: ...e Use B88 A 25 GTL I O A89 A 19 GTL I O B89 VCC_CORE Processor Core VCC A90 GND VSS B90 A 15 GTL I O A91 A 18 GTL I O B91 A 17 GTL I O A92 A 16 GTL I O B92 A 11 GTL I O A93 A 13 GTL I O B93 VCC_CORE P...

Page 167: ...T GTL I O A111 DBSY GTL I O B111 RS 2 GTL Input A112 RS 1 GTL Input B112 Reserved Reserved for Future Use A113 Reserved Reserved for Future Use B113 VCC_L2 Other VCC A114 GND VSS B114 RP GTL I O A115...

Page 168: ...35 GTL I O A96 A 10 GTL I O A5 A20M CMOS Input B92 A 11 GTL I O A115 ADS GTL I O B94 A 12 GTL I O B118 AERR GTL I O A93 A 13 GTL I O A117 AP 0 GTL I O A95 A 14 GTL I O B116 AP 1 GTL I O B90 A 15 GTL I...

Page 169: ...10 GTL I O A49 D 37 GTL I O A64 D 11 GTL I O B50 D 38 GTL I O B66 D 12 GTL I O A045 D 39 GTL I O A63 D 13 GTL I O B47 D 40 GTL I O A67 D 14 GTL I O B42 D 41 GTL I O B64 D 15 GTL I O A043 D 42 GTL I O...

Page 170: ...A111 DBSY GTL I O A34 GND VSS A105 DEFER GTL Input A38 GND VSS A25 DEP 0 GTL I O A042 GND VSS A27 DEP 1 GTL I O A46 GND VSS B26 DEP 2 GTL I O A50 GND VSS A28 DEP 3 GTL I O A54 GND VSS B27 DEP 4 GTL I...

Page 171: ...2 GTL Input B106 LOCK GTL I O B115 RSP GTL Input B18 PICCLK APIC Clock Input B101 SLOTOCC GND A19 PICD 0 CMOS I O B8 SLP CMOS Input B22 PICD 1 CMOS I O B3 SMI CMOS Input B23 PRDY GTL Output B6 STPCLK...

Page 172: ...C_L2 Other VCC B53 VCC_CORE Processor Core VCC A1 VCC_VTT GTL VTT Supply B57 VCC_CORE Processor Core VCC A3 VCC_VTT GTL VTT Supply B65 VCC_CORE Processor Core VCC B5 VCC_VTT GTL VTT Supply B69 VCC_COR...

Page 173: ...E 12 Boxed Processor Specifications...

Page 174: ......

Page 175: ...otherboard and system requirements for the fan heatsink that will be supplied with the Boxed Pentium II processor This chapter is particularly important for OEMs that manufacture motherboards for syst...

Page 176: ...ICATIONS This section documents the mechanical specifications of the Boxed Pentium II processor fan heatsink 12 2 1 Boxed Processor Fan Heatsink Dimensions The Boxed processor ships with an attached f...

Page 177: ...nnector Fan Heatsink S E C Cartridge Cover 000890a Figure 12 2 Side View Space Requirements for the Boxed Processor Fan heatsink supports not shown 4 90 Max D 1 25 2 19 C Power Cable Connector 000891a...

Page 178: ...t The Boxed processor fan heatsink will not weigh more than 225 grams See Chapter 10 and Chapter 11 for details on the processor weight and heatsink requirements 12 2 3 Boxed Processor Retention Mecha...

Page 179: ...n Table 12 2 Boxed Processor Fan Heatsink Support Dimensions Fig Ref Label Dimensions Inches Min Typ Max G Fan Heatsink support height 2 261 H Fan Heatsink support clearance above motherboard 0 430 J...

Page 180: ...Thru 0 187 Thru 2X Recommendations 0 300 dia trace keepout all external layers 0 250 dia trace keepout all internal layers All dimensions in inches 1 769 Slot 1 Connector 1 950 2 932 000875a Figure 12...

Page 181: ...E BOXED PROCESSOR SPECIFICATIONS 12 7 2 261 G 0 275 DIA J 0 300 MAX 0 240 K 1 769 0 060 L 0 060 M 0 430 H 000804a Figure 12 6 Side View Space Requirements for Boxed Processor Fan Heatsink Supports...

Page 182: ...he cable length is 7 0 inches 0 25 The fan heatsink outputs a SENSE signal which is an open collector output that pulses at a rate of two pulses per fan revolution A motherboard pull up resistor provi...

Page 183: ...header on motherboard Waldom Molex P N 22 23 2031 AMP P N 640456 3 or equivalent 1 2 3 GND 12V SENSE 1 2 3 000888 Figure 12 8 Boxed Processor Fan Heatsink Power Cable Connector Description Table 12 3...

Page 184: ...ized by the Boxed processor 12 4 1 Boxed Processor Cooling Requirements The Boxed processor is cooled with a fan heatsink The Boxed processor fan heatsink will keep the thermal plate temperature TPLAT...

Page 185: ...E 13 Integration Tools...

Page 186: ......

Page 187: ...arget Probe ITP for the Pentium II processor is a debug tool which allows access to on chip debug features via a small port on the system board called the debug port The ITP communicates to the proces...

Page 188: ...oard footprint The connectors are manufactured by AMP Incorporated and are in the AMPMODU System 50 line Following are the AMP part numbers for the two connectors Amp 30 pin shrouded vertical header 1...

Page 189: ...e entire target system The signal should be pulled up Intel recommends a 240 resistor but system designers will need to fine tune specific system designs to meet two considerations 1 the signal must b...

Page 190: ...or to Vcc2 5 at the point furthest from the debug port Poor routing can cause multiple clocking problems usually on falling edge of TCK Should be routed to all components in the boundary scan chain3 F...

Page 191: ...es requests to P0 to enter debug Add 150 to 330 ohm pull up resistor to Vcc2 5 PRDY0 18 PRDY0 signal driven by P0 informs ITP that P0 is ready for debug Terminate 2 signal properly at the debug port D...

Page 192: ...close as possible to the value specified 2 Termination should include a series 240 ohms and pull up connected to 1 5V resistors 3 Signal should be at end of daisy chain and the boundary scan chain sho...

Page 193: ...he number of loads on the TCK signal special care should be taken when routing it Poor routing can lead to multiple clocking of some agents on the debug chain usually on the falling edge of TCK This c...

Page 194: ...ts of data via boundary scan Additionally removing all but the processors from the boundary scan chain reduces the possibility for errors in the chain when using the ITP for system debug If the system...

Page 195: ...0 PREQ0 TDO TDI PRDY1 PREQ1 TDO BCLK BCLK TDO PREQ3 PRDY3 PREQ2 PRDY2 TCK TMS TRST BSEN DBRESET PREQ0 PRDY0 TDI DBINST POWERON PREQ1 PRDY1 RESET BCLK NOTE See Table 13 1 for recommended resistor value...

Page 196: ...lugged into the connector 13 1 5 2 DEBUG PORT CONNECTOR Figure 13 7 and Figure 13 8 illustrate how the debug port connector should be installed on a circuit board Note the way the pins are numbered on...

Page 197: ...TDI TDO PCIset PCIset 000799b Figure 13 9 Processor System where Boundary Scan is Not Used 13 2 INTEGRATION TOOL CONSIDERATIONS 13 2 1 Integration Tool Mechanical Keepouts An integration tool LAI562 h...

Page 198: ...s on the target system However due to the current limitations of some signal drivers this stronger value may not be feasible Calculation of the correct pull up resistor value for each of the CMOS sign...

Page 199: ...Edge Connector 0 025 Thermal Plate Side View All dimensions in inches 2 8 Integration Tool Volume 1 375 3 3 Cable continues up 000839c Figure 13 11 Pentium II Processor Integration Tool Mechanical Kee...

Page 200: ...14 PCB Slot 1 Edge Connector 0 025 Cover Side View All dimensions in inches 2 25 1 375 1 375 1 7 Integration Tool Volume 000840b Figure 13 12 Pentium II Processor Integration Tool Mechanical Keep Out...

Page 201: ...RATION TOOLS 13 15 Side View All dimensions in inches PCB 0 35 2 00 0 15 1 7 0 65 0 385 Cable continues upward 000838b Figure 13 13 Pentium II Processor Integration Tool Mechanical Keep Out Volume Sid...

Page 202: ......

Page 203: ...E 14 Advanced Features...

Page 204: ......

Page 205: ...oftware operating system kernels virtual memory managers BIOS and processor test software performance monitoring tools For software developers designing other categories of software this information d...

Page 206: ......

Page 207: ...E A Signals Reference...

Page 208: ......

Page 209: ...power on configuration A 1 2 A20M I If the A20M Address 20 Mask input signal is asserted the Pentium II processor masks physical address bit 20 A20 before looking up a line in any internal cache and...

Page 210: ...o the Machine Check Architecture MCA of the system A 1 5 AP 1 0 I O The AP 1 0 Address Parity signals are driven by the request initiator along with ADS A 35 3 REQ 4 0 and RP AP1 covers A 35 24 and AP...

Page 211: ...h was in transit is lost All agents reset their rotating ID for bus arbitration to the state after reset and internal count information is lost The L1 and L2 caches are not affected If BINIT observati...

Page 212: ...all of its requests are completed then releases the bus by deasserting BPRI A 1 13 BR0 I O BR1 I The BR0 and BR1 Bus Request pins drive the BREQ 1 0 signals in the system The BREQ 1 0 signals are int...

Page 213: ...he transfer order called burst order A line is transferred in four eight byte chunks each of which can be identified by address bits 4 3 The chunk size is 64 bits Table A 3 specifies the transfer orde...

Page 214: ...ctions A 1 16 DBSY I O The DBSY Data Bus Busy signal is asserted by the agent responsible for driving data on the Pentium II processor system bus to indicate that the data bus is in use The data bus i...

Page 215: ...LUSH is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O Write bus transac...

Page 216: ...nsaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until it is handled in software or with the assertion of RESET BINIT...

Page 217: ...oth signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by...

Page 218: ...rocessor and core logic or I O APIC which is required for operation of all processors core logic and I O APIC components on the APIC bus During FRC mode operation PICCLK must be 1 4 of and synchronous...

Page 219: ...h specification in Table 7 12 and be followed by a 1 ms RESET pulse The PWRGOOD signal must be supplied to the processor as it is used to protect internal circuits against voltage sequencing issues Th...

Page 220: ...t parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This definition allows parity to be high when all covered signals are high A 1...

Page 221: ...of the SLP STPCLK and RESET signals while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and APIC...

Page 222: ...cessor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The pro...

Page 223: ...th a 680 pull down resistor A 1 55 VID 4 0 O The VID 4 0 Voltage ID pins can be used to support automatic selection of power supply voltages These pins are not signals but are either an open circuit o...

Page 224: ...ut and I O signals Table A 5 Output Signals 1 Name Active Level Clock Signal Group FERR Low Asynch CMOS Output IERR Low Asynch CMOS Output PRDY Low BCLK GTL Output SLOTOCC Low Asynch Power Other TDO H...

Page 225: ...de NMI High Asynch CMOS Input APIC disabled mode PICCLK High APIC Clock Always PREQ Low Asynch CMOS Input Always PWRGOOD High Asynch CMOS Input Always RESET Low BCLK GTL Input Always RS 2 0 Low BCLK G...

Page 226: ...0 Low BCLK GTL I O DRDY DBSY Low BCLK GTL I O Always DEP 7 0 Low BCLK GTL I O DRDY DRDY Low BCLK GTL I O Always FRCERR High BCLK GTL I O Always LOCK Low BCLK GTL I O Always REQ 4 0 Low BCLK GTL I O A...

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