Intel Pentium II, Developer'S Manual

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TEST ACCESS PORT (TAP)
E
6-4
8/26/97 1:10 PM CH06.DOC
INTEL CONFIDENTIAL
(until publication date)
•
Pause-IR: Allows shifting of the instruction register to be temporarily halted. The
current instruction does not change.
•
Exit2-IR: This is a temporary state. The current instruction does not change.
•
Update-IR: The instruction which has been shifted into the Instruction Register is
latched onto the parallel output of the Instruction Register on the falling edge of TCK.
Once the new instruction has been latched, it remains the current instruction until the
next Update-IR (or until the TAP controller state machine is reset).
•
Select-DR-Scan: This is a temporary controller state. All registers retain their previous
values.
•
Capture-DR: In this state, the data register selected by the current instruction may
capture data at its parallel inputs.
•
Shift-DR: The Data Register connected between TDI and TDO as a result of selection
by the current instruction is shifted one stage toward its serial output on each rising edge
of TCK. The output arrives at TDO on the falling edge of TCK. The parallel, latched
output of the selected Data Register does not change while new data is being shifted in.
•
Exit1-DR: This is a temporary state. All registers retain their previous values.
•
Pause-DR: Allows shifting of the selected Data Register to be temporarily halted
without stopping TCK. All registers retain their previous values.
•
Exit2-DR: This is a temporary state. All registers retain their previous values.
•
Update-DR: Data from the shift register path is loaded into the latched parallel outputs
of the selected Data Register (if applicable) on the falling edge of TCK. This (and Test-
Logic-Reset) is the only state in which the latched paralleled outputs of a data register
can change.
6.2.1. Accessing the Instruction Register
Figure 6-3 shows the (simplified) physical implementation of the TAP instruction register.
This register consists of a 6-bit shift register (connected between TDI and TDO), and the
actual instruction register (which is loaded in parallel from the shift register). The parallel
output of the TAP instruction register goes to the TAP instruction decoder, shown in
Figure 6-1. This architecture conforms to the 1149.1 specification.