Intel Pentium II, Developer'S Manual

Page: 69 / 226

E
TEST ACCESS PORT (TAP)
6-5
8/26/97 1:10 PM CH06.DOC
INTEL CONFIDENTIAL
(until publication date)
Actual Instruction Register
Shift Register TDI TDO
Fixed Capture Value
Parallel Output (MSB) (LSB)
000942
Figure 6-3. Processor TAP Instruction Register
Figure 6-4 shows the operation of the TAP instruction register during the Capture-IR, Shift-
IR and Update-IR states of the TAP controller. Flip-flops within the instruction register
which are updated in each mode of operation are shaded. In Capture-IR, the shift register
portion of the instruction register is loaded in parallel with the fixed value “000001.” In
Shift-IR, the shift register portion of the instruction register forms a serial data path between
TDI and TDO. In Update-IR, the shift register contents are latched in parallel into the actual
instruction register. Note that the only time the outputs of the actual instruction register
change is during Update-IR. Therefore, a new instruction shifted into the TAP does not take
effect until the Update-IR state of the TAP controller is entered.
(a) Capture–IR
000943
(b) Shift–IR (c) Update–IR
000943
Figure 6-4. Operation of the Processor TAP Instruction Register
A timing diagram for loading the BYPASS instruction (op-code “111111”) into the TAP is
shown in Figure 6-5. (Note that the LSB of the TAP instruction must be shifted in first.)
Vertical arrows on the figure show the specific clock edges on which the Capture-IR, Shift-
IR and Update-IR actions actually take place. Capture-IR (which pre-loads the instruction