Intel Pentium II, Developer'S Manual

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E
ELECTRICAL SPECIFICATIONS
7-3
8/29/97 11:14 AM CH07.DOC
INTEL CONFIDENTIAL
(until publication date)
Due to the inability of processors to recognize bus transactions during Sleep state and Deep
Sleep state, two-way MP systems are not allowed to have one processor in Sleep/Deep Sleep
state and the other processor in Normal or Stop-Grant states simultaneously.
7.2.1. Normal State — State 1
This is the normal operating state for the processor.
7.2.2. Auto HALT Power Down State — State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction.
The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#,
INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately
initialize itself.
The return from the SMI handler can be to either Normal Mode or the AutoHALT Power
Down state. See the Intel Architecture Software Developer’s Manual, Volume III: System
Programming Guide (Order Number 243192) for more information.
FLUSH# will be serviced during AutoHALT state and the processor will return to the
AutoHALT state.
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down
state. When the system deasserts the STPCLK# interrupt, the processor will return execution
to the HALT state.
7.2.3. Stop-Grant State — State 3
The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted.
Since the GTL+ signal pins receive power from the system bus, these pins should not be
driven (allowing the level to return to V
TT
) for minimum power drawn by the termination
resistors in this state. In addition, all other input pins on the system bus should be driven to
the inactive state.
FLUSH# will be serviced during Stop-Grant state and the processor will return to the Stop-
Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay
in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of
the STPCLK# signal.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on
the system bus (see Section 7.2.4.). A transition to the Sleep state (see Section 7.2.6.) will
occur with the assertion of the SLP# signal.